Product Specification
PE42650A
Product Description
The following specification defines an SP3T (single pole three
throw) switch for use in cellular and other wireless applications.
It has both a standard and attenuated RX mode. The
PE42650A uses Peregrine’s UltraCMOS™ process and also
features HaRP™ technology enhancements to deliver high
linearity and exceptional harmonics performance. HaRP™
technology is an innovative feature of the UltraCMOS™
process providing upgraded linearity performance.
The PE42650A is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
SP3T High Power UltraCMOS™
RF Switch 30 MHz - 1000 MHz
Features
•
50 Watt P1dB compression point
•
10 Watts <8:1 VSWR (Normal
Operation)
•
38 dB TX-RX Isolation
•
2f
o
and 3f
o
< -81 dBc @10 Watts
•
ESD rugged to 2.0 kV HBM
•
No blocking capacitors required
•
32-lead 5x5 mm QFN package
Figure 1. Functional Diagram
ANT
O
CMOS
Control Driver
and ESD
Document No. 70-0267-02
│
www.psemi.com
BS
TX2
ESD
CTRL
O
TX1
ESD
ESD
LE
RX
TE
Figure 2. Package Type
32-lead 5x5 mm QFN
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE42650A
Product Specification
Table 1: Electrical Specifications @ +25 °C, V
DD
= 3.3 V
(Z
S
= Z
L
= 50
Ω
) unless otherwise noted
Parameter
TX Insertion Loss
1
RX Insertion Loss (Un-Attenuated State)
RX Insertion Loss (Attenuated State)
1
0.1 dB Input Compression Point
Isolation (Supply Biased): TX-TX
Isolation (Supply Biased): TX-RX
Unbiased Isolation: ANT - TX, V
DD
, V1,
V2, V3=0 V
Unbiased Isolation: ANT - RX, V
DD
, V1,
V2, V3=0 V
RX Port Return Loss
1
1
Conditions
30 MHz
≤
1 GHz
30 MHz
≤
1 GHz
800 MHz
800 MHz, 50% duty cycle
800 MHz
800 MHz
800 MHz, +27 dBm
800 MHz, +27 dBm
Un-Attenuated State, 800 MHz
Min
Typ
0.3
0.5
14.5
45.4
Max
0.5
0.9
16
Units
dB
dB
dB
dBm
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBm
13
30
35
6
33
38
Attenuated State, with external matching inductor optimized without
attenuator engaged, 800 MHz
800 MHz
800 MHz @ 42.5 dBm
800 MHz @ 42.5 dBm
TX and ANT Port Return Loss
1
TX, 2nd Harmonic
TX, 3rd Harmonic
RX IIP3
Switching Time
LE
Units
MHz
dBm
Un-Attenuated State, 800 MHz, 150 kHz tone separation
50% of CTRL to 10/90% of RF
TE
10
14
22
18
22
12
18
20
23
-81
-81
30
0.1
0.5
-79
-79
ms
Note: 1. The device was matched with ~4 nH inductance per RF port. RX port may not need matching inductor.
Table 2. Operating Ranges
Parameter
Frequency Range
TX Input Power
1
(VSWR
≤
8:1)
RX Input Power
2
(VSWR
≤
8:1)
V
DD
Power Supply Voltage
I
DD
Power Supply Current
Control Voltage High
Control Voltage Low
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
O
Min
30
Typ
Max
40
Parameter/Conditions
Min Max Units
-0.3
-0.3
-65
4
V
DD
+
0.3
150
85
200
40
45
27
27
2.8
2000
V
V
°C
°C
°C
dBm
dBm
dBm
dBm
W
V
1000
Power supply voltage
Voltage on any DC input
Storage temperature range
Maximum case temperature
Peak maximum junction
temperature (10 seconds max)
TX Input Power
1
(VSWR 20:1, 10 seconds)
TX Input Power
1
(50
Ω)
RX Input Power at ANT pin
2
(VSWR 20:1)
RF Input Power on inactive ports or
supply unbiased
27
dBm
V
BS
90
170
1.4
0.4
85
-40
140
3.2
3.3
3.4
T
CASE
T
j
uA
V
V
T
OP
Operating temperature
range (Case)
T
j
Operating junction
temperature
°C
°C
P
IN
O
Notes: 1. Supply biased
2. Supply biased or unbiased
P
D
V
ESD
Maximum Power Dissipation from
RF Insertion Loss
ESD Voltage (HBM, MIL_STD 883
Method 3015.7)
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE42650A
in the 5x5 QFN package is MSL3.
Notes: 1. Supply biased
2. Supply biased or unbiased
Absolute Maximum Ratings
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. 70-0267-02
│
UltraCMOS™ RFIC Solutions
PE42650A
Product Specification
Figure 3. Pin Configuration (Top View)
32
GND
31
GND
30
GND
29
GND
27
GND
26
GND
25
GND
28
ANT
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
GND
TX1
GND
TX1
GND
GND
GND
RX
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
9
24
GND
23
TX2
22
GND
21
TX2
20
GND
19
GND
18
GND
17
GND
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
V3
V2
GND
GND
Vdd
N/C
V1
N/C
TE
Path
V3
L
L
L
L
H
H
H
H
Exposed
Ground
Paddle
Latch-Up Avoidance
LE
ANT – RX Attenuated
Unsupported mode
Unsupported mode
ANT – TX1
ANT – RX
Unsupported mode
Unsupported mode
ANT – TX2
V2
L
L
H
H
L
L
H
H
V1
L
H
L
H
L
H
L
H
Table 4. Pin Descriptions
Pin No.
1
2
3
4
5-7
8
9-10
11
12
Pin Name
GND
TX1
GND
TX1
1
GND
RX
GND
N/C
V
DD
V3
V2
Ground
TX1 port
Ground
TX1 port
Ground
Description
RX port
Ground
No Connect
17-20
21
O
23
TX2
3
24-27
28
GND
ANT
29-32
GND
Paddle
GND
Note: 1. Must be tied to pin 2
2. Must be tied to V2
3. Must be tied to pin 21
Document No. 70-0267-02
│
www.psemi.com
BS
Nominal 3.3 V supply connection
13
14
15
16
Control
Control
V1
2
Control
N/C
Do not connect
Ground
GND
TX2
TX2 port
22
GND
Ground
TX2 port
Ground
Antenna Port
Ground
Exposed ground paddle
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
O
PE42650A
Product Specification
Evaluation Kit
The PE42650A Evaluation Kit board was designed
to ease customer evaluation of the PE42650A RF
switch.
DC power is supplied through J10, with V
DD
on pin 9,
and GND on the entire lower row of even numbered
pins. To evaluate a switch path, add or remove
jumpers on V1 (pin 3), V2 (pin 5), and V3 (pin
7) using Table 5 (adding a jumper pulls the CMOS
control pin low and removing it allows the on-board
pull-up resistor to set the CMOS control pin
high). J10 pins 1, 11, and 13 are N/C.
The RF common port (ANT) is connected through
a 50 Ohm transmission line via the top SMA
connector, J1. RX and TX paths are also
connected through 50 Ohm transmission lines via
SMA connectors. A 50 Ohm through transmission
line is available via SMA connectors J8 and J9.
This transmission line can be used to estimate the
loss of the PCB over the environmental conditions
being evaluated. An open-ended 50 Ohm
transmission line is also provided at J7 for calibration
if needed.
Narrow trace widths are used near each part to
improve impedance matching.
Figure 4. Evaluation Board Layout
Peregrine Specification 101-0315
O
O
BS
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. 70-0267-02
│
UltraCMOS™ RFIC Solutions
LE
Figure 5. Evaluation Board Schematic
Peregrine Specification 102-0535
TE
PE42650A
Product Specification
Performance Plots
Figure 6. Isolation, Tx-Tx, V
DD
=3.3V
Figure 8. Isolation, Tx-Tx, +25°C
Figure 7. Isolation, Tx-Rx, V
DD
=3.3V
O
Document No. 70-0267-02
│
www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
BS
O
LE
Figure 9. Isolation, Tx-Rx, +25°C
TE
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