CAT93C46R
1K-Bit Microwire Serial EEPROM
FEATURES
I
High speed operation: 1MHz
I
Low power CMOS technology
I
1.8 to 5.5 volt operation
I
Selectable x8 or x16 memory organization
I
Self-timed write cycle with auto-clear
I
Hardware and software write protection
I
Power-up inadvertant write protection
I
1,000,000 Program/erase cycles
I
100 year data retention
I
Industrial temperature range
I
RoHS compliant
DESCRIPTION
The CAT93C46R is a 1K-bit Serial EEPROM memory
device which is configured as either registers of 16 bits
(ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C46R is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The device is available in 8-pin DIP, 8-pin SOIC,
8-pin TSSOP and 8-pad TDFN packages.
“
”
&
“
”
8-pin PDIP, SOIC, TSSOP and TDFN packages
PIN CONFIGURATION
DIP Package (L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
FUNCTIONAL SYMBOL
SOIC Package (W)
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
V
CC
ORG
CS
SK
NC
DI
DO
SOIC Package (V)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
CS
SK
DI
DO
SOIC Package (X)
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
GND
PIN FUNCTIONS
Pin Name
CS
SK
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+1.8V to 5.5V Power Supply
Ground
Memory Organization
No Connection
TSSOP Package (Y)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
DI
DO
V
CC
GND
TDFN Package (ZD4)
VCC
8
NC
7
ORG
6
GND
5
1
CS
2
SK
3
DI
4
DO
ORG
NC
Bottom View
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1107, Rev. C
CAT93C46R
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Voltage on Any Pin with Respect to Ground
(1)
*
-65°C to +150°C
-0.5 V to +6.5 V
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
(2)
Symbol
N
END
(*)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V
I
OH
= -100µA
V
CC
- 0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
0
Min
Typ
Max
3
500
10
10
2
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 1107, Rev. C
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C46R
POWER-UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C46R is a 1024-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C46R can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 9-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 10-bit instructions control the reading, writing and
erase operations of the device. The CAT93C46R oper-
ates on a single power supply and will generate on chip,
the high voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (t
PD0
or t
PD1
).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Doc. No. 1107, Rev. C
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
