MX29LV160T/B & MX29LV160AT/AB
16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 2,097,152 x 8/1,048,576 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase Suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.
• CFI (Common Flash Interface) compliant (for
MX29LV160AT/AB)
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 1.4V
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP (8x13mm:for MX29LV160T/B; 6x8mm:
for MX29LV160AT/AB)
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
power supply levels during erase and programming, while
maintaining maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV160T/B & MX29LV160AT/AB uses a
2.7V~3.6V VCC supply to perform the High Reliability
Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
Part Name
MX29LV160T/B
MX29LV160AT/AB
Difference
1) Without CFI compliant
2)CSP dimension:8x13mm
1) With CFI compliant
2)CSP dimension:6x8mm
REV. 3.7, APR. 23, 2003
GENERAL DESCRIPTION
The MX29LV160T/B & MX29LV160AT/AB is a 16-mega
bit Flash memory organized as 2M bytes of 8 bits or 1M
words of 16 bits. MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX29LV160T/B & MX29LV160AT/
AB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball
CSP. It is designed to be reprogrammed and erased in
system or in standard EPROM programmers.
The standard MX29LV160T/B & MX29LV160AT/AB of-
fers access time as fast as 70ns, allowing operation of
high-speed microprocessors without wait states. To elimi-
nate bus contention, the MX29LV160T/B &
MX29LV160AT/AB has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV160T/B & MX29LV160AT/AB uses a command
register to manage this functionality. The command reg-
ister allows for 100% TTL level control inputs and fixed
P/N:PM0866
1
FPGA/CPLD
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