MX29LV320AT/B
32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• 4,194,304 x 8 / 2,097,152 x 16 switchable
• Sector Structure
- 8K-Byte x 8 and 64K-Byte x 63
• Extra 64K-Byte sector for security
- Features factory locked and identifiable, and cus-
tomer lockable
• Twenty-Four Sector Groups
- Provides sector group protect function to prevent pro-
gram or erase operation in the protected sector group
- Provides chip unprotect function to allow code chang-
ing
- Provides temporary sector group unprotect function
for code changing in previously protected sector groups
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit is equal to or less than 1.4V
• Compatible with JEDEC standard
- Pinout and software compatible to single power sup-
ply Flash
•
2nd generation of 3V/32M Flash product
- Fully compatible with MX29LV320T/B device
PERFORMANCE
• High Performance
- Fast access time: 70/90ns
- Fast program time: 7us/word typical utilizing acceler-
ate function
- Fast erase time: 0.9s/sector, 35s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
• Status Reply
- Data polling & Toggle bits provide detection of pro-
gram and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy (RY/BY) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET) Input
- Provides a hardware method to reset the internal state
machine to read mode
• WP/ACC input pin
- Provides accelerated program capability
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP
GENERAL DESCRIPTION
The MX29LV320AT/B is a 32-mega bit Flash memory
organized as 4M bytes of 8 bits and 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV320AT/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29LV320AT/B offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV320AT/B has separate chip enable (CE)
and output enable (OE) controls.
P/N:PM1008
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV320AT/B uses a command register to manage
this functionality.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
REV. 1.1, MAY 28, 2004
1
MX29LV320AT/B
The MX29LV320AT/B uses a 2.7V to 3.6V VCC
supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamperes on address and data pin from -1V to
VCC + 1V.
modes allow sectors of the array to be erased in one
erase cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29LV320AT/B elec-
trically erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes/words are programmed by
using the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING
The MX29LV320AT/B is byte/word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the
data programmed. The typical chip programming time at
room temperature of the MX29LV320AT/B is less than
36 seconds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 35 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV320AT/B is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. Sector erase
P/N:PM1008
REV. 1.1, MAY 28, 2004
2
MX29LV320AT/B
PIN CONFIGURATION
48 TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
MX29LV320AT/B
48-Ball CSP 6mm x 8mm (Ball Pitch = 0.8 mm), Top View, Balls Facing Down
A
B
C
D
E
F
G
H
6
5
4
3
2
1
A13
A9
WE
A12
A8
RESET
A14
A10
NC
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
Q7
Q5
Q2
Q0
A0
BYTE
Q14
Q12
Q10
Q8
CE
Q15/A-1 GND
Q13
Vcc
Q11
Q9
OE
Q6
Q4
Q3
Q1
GND
RY/BY WP/ACC
A7
A3
A17
A4
PIN DESCRIPTION
SYMBOL
A0~A20
Q0~Q14
Q15/A-1
CE
WE
OE
BYTE
RESET
RY/BY
VCC
WP/ACC
GND
NC
P/N:PM1008
LOGIC SYMBOL
21
A0-A20
Q0-Q15
(A-1)
16 or 8
PIN NAME
Address Input
15 Data Inputs/Outputs
Q15(Data Input/Output, word mode)
A-1(LSB Address Input, byte mode)
Chip Enable Input
Write Enable Input
Output Enable Input
Word/Byte Selection Input
Hardware Reset Pin, Active Low
Read/Busy Output
3.0 volt-only single power supply
Hardware Write Protect/Acceleration
Pin
Device Ground
Pin Not Connected Internally
CE
OE
WE
RESET
BYTE
WP/ACC
RY/BY
REV. 1.1, MAY 28, 2004
3
MX29LV320AT/B
BLOCK DIAGRAM
CE
OE
WE
RESET
BYTE
WRITE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX29LV320AT/B
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A20
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM1008
REV. 1.1, MAY 28, 2004
4
MX29LV320AT/B
Table 1.a: MX29LV320AT SECTOR GROUP ARCHITECTURE
Sector
Group
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
P/N:PM1008
Sector Sector Address
A20-A12
SA0
000000xxx
SA1
000001xxx
SA2
000010xxx
SA3
000011xxx
SA4
000100xxx
SA5
000101xxx
SA6
000110xxx
SA7
000111xxx
SA8
001000xxx
SA9
001001xxx
SA10
001010xxx
SA11
001011xxx
SA12
001100xxx
SA13
001101xxx
SA14
001110xxx
SA15
001111xxx
SA16
010000xxx
SA17
010001xxx
SA18
010010xxx
SA19
010011xxx
SA20
010100xxx
SA21
010101xxx
SA22
010110xxx
SA23
010111xxx
SA24
011000xxx
SA25
011001xxx
SA26
011010xxx
SA27
011011xxx
SA28
011100xxx
SA29
011101xxx
SA30
011110xxx
SA31
011111xxx
SA32
100000xxx
SA33
100001xxx
SA34
100010xxx
SA35
100011xxx
SA36
100100xxx
SA37
100101xxx
SA38
100110xxx
SA39
100111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(x8)
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
(x16)
Address Range
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
REV. 1.1, MAY 28, 2004
5
FPGA/CPLD
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