MX29LV320C T/B
32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• 4,194,304 x 8 / 2,097,152 x 16 switchable
• Sector Structure
- 8K-Byte x 8 and 64K-Byte x 63
• Extra 64K-Byte sector for security
- Features factory locked and identifiable, and cus-
tomer lockable
• Twenty-Four Sector Groups
- Provides sector group protect function to prevent pro-
gram or erase operation in the protected sector group
- Provides chip unprotect function to allow code chang-
ing
- Provides temporary sector group unprotect function
for code changing in previously protected sector groups
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit is equal to or less than 1.4V
• Compatible with JEDEC standard
- Pinout and software compatible to single power sup-
ply Flash
•
Fully compatible with MX29LV320A T/B device
PERFORMANCE
• High Performance
- Fast access time: 70/90ns
- Fast program time: 7us/word typical utilizing acceler-
ate function
- Fast erase time: 0.9s/sector, 35s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
• Status Reply
- Data# Polling & Toggle bits provide detection of pro-
gram and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state
machine to read mode
• WP#/ACC input pin
- Provides accelerated program capability
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP
•
All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
The MX29LV320C T/B is a 32-mega bit Flash memory
organized as 4M bytes of 8 bits and 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV320C T/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29LV320C T/B offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV320C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
P/N:PM1188
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV320C T/B uses a command register to manage
this functionality.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
REV. 1.0, AUG. 02, 2005
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MX29LV320C T/B
cycling. The MX29LV320C T/B uses a 2.7V to 3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved with
MXIC's proprietary non-epi process. Latch-up protection
is proved for stresses up to 100 milliamperes on address
and data pin from -1V to VCC + 1V.
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of electri-
cal erase are controlled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the sta-
tus of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29LV320C T/B elec-
trically erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes/words are programmed by
using the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING
The MX29LV320C T/B is byte/word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the
data programmed. The typical chip programming time at
room temperature of the MX29LV320C T/B is less than
36 seconds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to Data# Polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 35 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV320C T/B is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. Sector erase
modes allow sectors of the array to be erased in one
erase cycle. The Automatic Sector Erase algorithm
P/N:PM1188
REV. 1.0, AUG. 02, 2005
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