MX29LV640T/B
FEATURES
64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY
FLASH MEMORY
SOFTWARE FEATURES
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
• Status Reply
- Data polling & Toggle bits provide detection of pro-
gram and erase operation completion
GENERAL FEATURES
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• 8,388,608 x 8 / 4,194,304 x 16 switchable
• Sector structure
- 8KB (4KW) x 8 and 64KB(32KW) x 127
• Sector Protection/Chip Unprotect
- Provides sector group protect function to prevent
program or erase operation in the protected sector
group
- Provides chip unprotect function to allow code
changes
- Provides temporary sector group unprotect function
for code changes in previously protected sector groups
• Secured Silicon Sector
- Provides a 128-word area for code or data that can
be permanently protected.
- Once this sector is protected, it is prohibited to pro-
gram or erase within the sector again.
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit is equal to or less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power sup-
ply Flash
PERFORMANCE
• High Performance
- Fast access time: 90/120ns
- Fast program time: 11us/word, 45s/chip (typical)
- Fast erase time: 0.9s/sector, 45s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 0.2uA (typ.)
• Minimum 100,000 erase/program cycle
• 20-year data retention
HARDWARE FEATURES
• Ready/Busy (RY/BY) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP Pin
- Write protect (WP) function allows protection of two
outermost boot sectors, regardless of sector protect
status
PACKAGE
• 48-pin TSOP
• 63-ball CSP
• 64-ball Easy BGA
GENERAL DESCRIPTION
The MX29LV640T/B is a 64-mega bit Flash memory or-
ganized as 8M bytes of 8 bits or 4M bytes of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV640T/B is packaged in 48-pin TSOP, 63-
ball CSP and 64-ball Easy BGA. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV640T/B offers access time as fast
as 90ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV640T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
P/N:PM0920
REV. 1.2, NOV. 05, 2003
1
MX29LV640T/B
MX29LV640T/B uses a command register to manage this
functionality.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LV640T/B uses a 2.7V to 3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
AUTOMATIC SECTOR ERASE
The MX29LV640T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV640T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING
The MX29LV640T/B is byte/word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the
data programmed. The typical chip programming time at
room temperature of the MX29LV640T/B is less than 50
seconds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 115 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
P/N:PM0920
REV. 1.2, NOV. 05, 2003
2
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
