Orientation of Top Mark determines Pin One location. Read the top product
code mark left to right, Pin One is the lower left pin (see diagram).
Function Table
Input (S)
L
H
H HIGH Logic Level
L LOW Logic Level
Pin Descriptions
Function
B
0
Connected to A
B
1
Connected to A
Pin Names
A, B
0
, B
1
S
Description
Data Ports
Control Input
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2
NC7SBU3157 • FSAU3157
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
) (Note 2)
DC Input Voltage (V
IN
) (Note 2)
DC Input Diode Current (I
IK
)
@ (I
IK
) V
IN
0V
DC Output Current (I
OUT
)
DC V
CC
or Ground Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
Junction Temperature under Bias (T
J
)
Junction Lead Temperature (T
L
)
Power Dissipation (P
D
) @
85
q
C
(Soldering, 10 seconds)
0.5V to
7.0V
0.5V to V
CC
0.5V
0.5V to
7.0V
50 mA
r
100 mA
65
q
C to
150
q
C
150
q
C
260
q
C
180 mW
128 mA
Recommended Operating
Conditions
(Note 3)
Supply Voltage Operating (V
CC
)
Control Input Voltage (V
IN
)
Switch Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
A
)
Input Rise and Fall Time (t
r
, t
f
)
Control Input V
CC
Control Input V
CC
2.3V - 3.6V
4.5V - 5.5V
0 ns/V to 10 ns/V
0 ns/V to 5 ns/V
350
q
C/W
1.65V to 5.5V
0V to V
CC
0V to V
CC
0V to V
CC
40
q
C to
85
q
C
Thermal Resistance (
T
JA
)
Note 1:
Absolute maximum ratings are DC values beyond which the device may be
damaged or have its useful life impaired. The datasheet specifications should be met,
without exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recommend oper-
ation outside datasheet specifications.
Note 2:
The input and output negative voltage ratings may be exceeded if the input
and output diode current ratings are observed.
Note 3:
Control input must be held HIGH or LOW, it must not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
I
IN
I
OZ
R
ON
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
Input Leakage Current
OFF State Leakage Current
Switch On Resistance
(Note 4)
4.5
V
CC
(V)
1.65
1.95
2.3
5.5
1.65
1.95
2.3
5.5
0
5.5
1.65
5.5
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Units
Conditions
Min
0.75 V
CC
0.7 V
CC
V
0.25 V
CC
0.3 V
CC
V
r
0.05
r
0.05
3.0
5.0
7.0
4.0
10.0
5.0
13.0
6.5
17.0
r
0.1
r
0.1
15.0
15.0
15.0
20.0
20.0
30.0
30.0
50.0
50.0
1.0
r
1
r
1
15.0
15.0
15.0
20.0
20.0
30.0
30.0
50.0
50.0
10.0
0
V
CC
25.0
50.0
100
300
P
A
P
A
:
:
:
:
:
:
:
:
:
P
A
V
0
d
V
IN
d
5.5V
0
d
A, B
d
V
CC
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
I
OUT
I
A
0V, I
O
2.4V, I
O
4.5V, I
O
0V, I
O
3V, I
O
0V, I
O
2.3V, I
O
0V, I
O
1.65V, I
O
0
30 mA
30 mA
30 mA
24 mA
3.0
2.3
1.65
I
CC
Quiescent Supply Current
All Channels ON or OFF
Analog Signal Range
R
RANGE
On Resistance
Over Signal Range
(Note 4)(Note 8)
5.5
V
CC
4.5
3.0
2.3
1.65
4.5
3.0
2.3
1.65
V
IKU
R
flat
Voltage Undershoot
On Resistance Flatness
(Note 4)(Note 5)(Note 7)
5.5
5.0
3.3
2.5
1.8
0
24 mA
8 mA
8 mA
4 mA
4 mA
V
CC
or GND
V
CC
30 mA, 0
d
V
Bn
d
V
CC
24 mA, 0
d
V
Bn
d
V
CC
8 mA, 0
d
V
Bn
d
V
CC
4 mA, 0
d
V
Bn
d
V
CC
30 mA, V
Bn
8 mA, V
Bn
4 mA, V
Bn
3.15
1.6
1.15
:
I
A
I
A
I
A
I
A
I
A
I
A
I
A
'
R
ON
On Resistance Match
Between Channels
(Note 4)(Note 5)(Note 6)
0.15
0.2
0.5
0.5
:
24 mA, V
Bn
2.1
2.0
6.0
12.0
28.0
125
V
0.0 mA
t
I
IN
t
50 mA, OE 5.5V
I
A
30 mA, 0
d
V
Bn
d
V
CC
24 mA, 0
d
V
Bn
d
V
CC
8 mA, 0
d
V
Bn
d
V
CC
4 mA, 0
d
V
Bn
d
V
CC
:
I
A
I
A
I
A
Note 4:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A
or B Ports).
Note 5:
Parameter is characterized but not tested in production.
Note 6:
'
R
ON
R
ON
max
R
ON
min measured at identical V
CC
, temperature and voltage levels.
3
www.fairchildsemi.com
NC7SBU3157 • FSAU3157
DC Electrical Characteristics
Note 8:
Guaranteed by Design.
(Continued)
Note 7:
Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions.
AC Electrical Characteristics
Symbol
t
PHL
t
PLH
Parameter
Propagation Delay
Bus to Bus
(Note 10)
t
PZL
t
PZH
Output Enable Time
Turn on Time
(A to B
n
)
t
PLZ
t
PHZ
Output Disable Time
Turn Off Time
(A Port to B Port)
t
B-M
V
CC
(V)
1.65
1.95
2.3
2.7
3.0
3.6
4.5
5.5
1.65
1.95
2.3
2.7
3.0
3.6
4.5
5.5
1.65
1.95
2.3
2.7
3.0
3.6
4.5
5.5
Break Before Make Time 1.65
1.95
(Note 9)
2.3
2.7
3.0
3.6
4.5
5.5
Q
OIRR
Xtalk
BW
THD
Charge Injection (Note 9)
Off Isolation (Note 11)
Crosstalk
5.0
3.3
1.65
5.5
1.65
5.5
1.65
5.5
7.0
3.5
2.5
1.7
3.0
2.0
1.5
0.8
0.5
0.5
0.5
0.5
7.0
3.0
1.2
0.8
0.3
23.0
13.0
6.9
5.2
12.5
7.0
5.0
3.5
7.0
3.5
2.5
1.7
3.0
2.0
1.5
0.8
0.5
0.5
0.5
0.5
pC
dB
dB
MHz
C
L
R
L
f
R
L
f
R
L
R
L
5
0.011
%
f
Note 9:
Guaranteed by Design.
Note 10:
This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and
the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Note 11:
Off Isolation
20 log
10
[V
A
/ V
Bn
]
0.1 nF, V
GEN
0
:
50
:
10MHz
50
:
10MHz
50
:
600
:
20 Hz to 20 KHz
0V
R
GEN
Figure 5
Figure 6
Figure 7
Figure
10
ns
Figure 4
1.2
0.8
0.3
24.0
14.0
7.6
5.7
13.0
7.5
5.3
3.8
ns
V
I
V
I
2 x V
CC
for t
PLZ
0V for t
PHZ
Figures
2, 3
ns
V
I
V
I
2 x V
CC
for t
PZL
0V for t
PZH
Figures
2, 3
ns
V
I
OPEN
Figures
2, 3
Min
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Units
Conditions
Figure
Number
Min
57.0
54.0
250
3dB Bandwidth
Total Harmonic Distortion
(Note 9)
0.5 V
P-P
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4
NC7SBU3157 • FSAU3157
Capacitance
Symbol
C
IN
C
IO-B
C
IOA-ON
Note 12:
T
A
(Note 12)
Figure
Number
Figure 8
Figure 9
Parameter
Control Pin Input Capacitance
B Port Off Capacitance
A Port Capacitance When Switch Is Enabled
Typ
2.3
6.5
18.5
Max
Units
pF
pF
pF
Conditions
V
CC
V
CC
V
CC
0V
5.0V
5.0V
25
q
C, f
1 MHz, Capacitance is characterized but not tested in production.
Undershoot Characteristic
(Note 13)
Symbol
V
OUTU
Parameter
Output Voltage During Undershoot
Min
2.5
Typ
V
OH
- 0.3
Max
Units
V
Conditions
Figure 1
Note 13:
This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event.
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