NCP1231
Low−Standby Power High
Performance PWM
Controller
The NCP1231 represents a major leap towards achieving low
standby power in medium−to−high power Switched−Mode Power
Supplies such as notebook adapters, off−line battery chargers and
consumer electronics equipment. Housed in SOIC−8 or PDIP−8, the
NCP1231 contains all needed control functionality to build a rugged
and efficient power supply. Among the unique features offered by the
NCP1231 is an event management scheme that can disable the
front−end PFC circuit during standby, thus reducing the no load power
consumption. The NCP1231 itself goes into cycle skipping at light
loads while limiting peak current (to 25% of nominal peak) so that no
acoustic noise is generated and while in the skip cycle mode.
The NCP1231 also features an internal latching function that can be
used for Overvoltage Protection (OVP). The latch is triggered when
the voltage on Pin 8 rises above 4.0 V. During an OVP condition, the
output drive pulses are immediately stopped and the NCP1231 stays in
the latched off condition until V
CC
drops below 4.0 V (V
CCreset
). In
addition, Pin 8 also serves as a Brown−Out input which provides the
necessary safety feature when the SMPS faces low mains situations.
Features
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
1
8
PDIP−8
P SUFFIX
CASE 626
1
1
1231Pzz
AWL
YYWWG
231Dx
y
ALYW
G
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current−Mode Operation with Internal Ramp Compensation
Extremely Low Startup Current
of 30
mA
Typical
Skip−Cycle Capability at Low Peak Currents
Adjustable Soft−Start
Overvoltage
and
Brown−Out Protection
Short−Circuit Protection Independent of Auxiliary Level
Internal Frequency Dithering for Improved EMI Signature
Go−To−Standby Signal for PFC Front Stage
Extremely Low No−Load, Noiseless, Standby Power
Internal Leading Edge Blanking
+500 mA/−800 mA Peak Current Drive Capability
Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz
Direct Optocoupler Connection
SPICE Models Available for TRANsient and AC Analysis
Pb−Free Packages are Available
= Device Code
x = 1 or 6
y = 0 or 3
1231Pzz = Device Code
zz = 65, 100 or 133
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
or G
= Pb−Free Package
231Dxy
PIN CONNECTIONS
PFC_V
CC
FB
CS
GND
1
8
BO/OVP
SS
V
CC
DRV
Typical Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
•
High Power AC−DC Adapters for Notebooks, etc.
•
Offline Battery Chargers
•
Set−Top Boxes Power Supplies, TV, Monitors, etc.
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 4
1
Publication Order Number:
NCP1231/D
NCP1231
HV
OVP
+
BO/OVP
to PFC’s V
CC
+
1
2
3
4
NCP1231
8
7
6
5
SS
GND
V
out
Ramp
GND
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
1
Pin Name
PFC V
CC
Function
Directly powers the PFC
front−end stage
Pin Description
This pin is a direct connection to the V
CC
pin (Pin 6) via a low impedance switch.
In standby and during the startup sequence, the switch is open and the PFC V
CC
is shutdown. As soon as the aux. winding is stabilized, Pin 1 connects to the V
CC
pin and provides bias to the PFC controller. It goes down in standby and fault
conditions.
An optocoupler collector pulls this pin low to regulate. When the current setpoint
falls below 25% of the maximum peak, the controller skips cycles.
This pin incorporates two different functions: the standard sense function and an
internal ramp compensation signal.
−
With a drive capability of +500 mA /
−800
mA, the NCP1231 can drive large Qg
MOSFETs.
The controller accepts voltages up to 18 V and features a UVLO of 7.7 V typical.
This pin provides three different functions, via a capacitor to ground, saw tooth
signal whose function is to create a soft−start, frequency dithering and 100 msec
fault timer.
By connecting this pin to a resistive divider, the controller ensures operation at a
safe mains level. If an external event brings this pin above 4 V, the controller is
permanently latched−off.
2
3
4
5
6
7
FB
CS
GND
DRV
V
CC
SS
(Soft−Start)
BO/OVP
Feedback Signal
Current Sense
IC Ground
Driver Output
V
CC
Input
To provide an internal
ramp timing for different
usages
Brown−Out and OVP
8
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2
SW1
Latchoff
4.2 Vdc
8
S
+
Q R
Brown Out
+
0.5/0.23 Vdc
10 V
−
Skip
Low Power
Vcc Mgmt
Vccoff=12.6V
Vccmin=7.7V
−
4Vcomp
+
−
Fault
Thermal
Shutdown
4.0 Vdc
Vdd Internal
Bias
Vdd
4Vdc
+
−
Vdd
1
mA
−
+
10 V
+
−
2.2 Vdc
R
OSC
2.3 Vpp
Ramp
S
500
mA
Q
60
mA
V
CC
20 V
6
Frequency
Modulation
/Soft−Start
/Timer
PWM
60
mA
SS
7
BO/OVP
1
PFC_Vcc
+
0.75 Vdc
−
PFC_Vcc
PFC_Vcc
Vccreset
−
100 msec
Timer
1.25 Vdc
+
Vdd
20k
Error
NCP1231
Figure 2. Internal Circuit Architecture
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3
2
FB
55k
10 V
25k
+
−
Soft−Start Ramp (1 V max)
3
CS
18 k
LEB
DRV
5
10 V
4
GND
NCP1231
MAXIMUM RATINGS
(Notes 1 and 2)
Rating
Voltage BO/OVP Pin 8
Current
Voltage Pin 7
Current
Power Supply Voltage, Pin 6
Maximum Current
Drive Output Voltage, Pin 5
Drive Current
Voltage Current Sense Pin, Pin 3
Current
Voltage Feedback, Pin 2
Current
Voltage, Pin 1
Maximum Continuous Current Flowing from Pin 1
Thermal Resistance, Junction−to−Air, PDIP Version
Thermal Resistance, Junction−to−Air, SOIC Version
Maximum Power Dissipation @ T
A
= 25°C
Maximum Junction Temperature
Storage Temperature Range
PDIP
SOIC
Symbol
BO/OVP
SS
V
CC
I
C
V
DV
I
o
V
cs
I
cs
V
fb
I
fb
V
PFC
I
PFC
R
qJA
R
qJA
P
max
T
J
T
stg
Value
10
100
10
100
−0.3
to 18
100
18
1.0
10
100
10
100
18
35
100
178
1.25
0.702
150
−60
to +150
Unit
V
mA
V
mA
V
mA
V
A
V
mA
V
mA
V
mA
°C/W
°C/W
W
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−6: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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4
NCP1231
V
CC
= 13 V, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
=
−40°C
to +125°C, Max T
J
= 150°C,
Rating
Supply Section
(All frequency versions, otherwise noted)
Turn−On Threshold Level, V
CC
going up (V
fb
= 2.0 V)
Minimum Operating Voltage after Turn−On
V
CC
Level at which the Internal Logic gets Reset (Note 4)
Startup Current (V
CCON
−0.2
V)
Internal IC Consumption, No Output Load on Pin 6 (V
fb
= 2.5 V)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
SW
= 65 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
SW
= 100 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
SW
= 133 kHz
Internal IC Consumption, Latch−Off Phase
Drive Output
Output Voltage Rise−Time @ C
L
= 1.0 nF, 10−90% of Output Signal (Note 4)
Output Voltage Fall−Time @ C
L
= 1.0 nF, 10−90% of Output Signal (Note 4)
Source Resistance (R
Load
= 300
W,
V
fb
= 2.5 V)
Sink Resistance, at 1.0 V on Pin 5 (V
fb
= 3.5 V)
Pin1 Output Impedance (or R
dson
between Pin 1 and Pin 6 when SW1 is closed)
R
load
on Pin 1= 680
W
Current Comparator
(Pin 5 unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Set Point
T
J
= +25°C
T
J
=
−40°C
to +125°C
I
IB
I
Limit
V
skip
V
stby−out
T
DEL CS
T
LEB
f
OSC
f
OSC
f
OSC
−
−
D
max
SS
−
−
−
−
3
3
3
−
3
3
−
0.95
0.93
600
1.0
−
100
0.02
1.00
−
750
1.25
90
250
−
1.05
1.07
900
1.5
200
350
mA
V
mV
V
ns
ns
T
r
T
f
R
OH
R
OL
RPFC
5
5
5
5
1
−
−
6.0
3.0
6.0
40
15
12.3
7.5
11.7
−
−
25
18
23
ns
ns
W
W
W
V
CCON
V
CC(min)
V
CCreset
I
startup
I
CC1
I
CC2
I
CC2
I
CC2
I
CC3
6
6
6
6
6
6
6
6
6
11.3
7.0
−
−
0.75
1.4
1.4
1.4
300
12.6
7.7
4.0
30
1.3
2.0
2.4
2.9
500
13.8
8.4
−
50
2.0
2.6
3.1
3.7
800
V
V
V
mA
mA
mA
mA
mA
mA
Symbol
Pin
Min
Typ
Max
Unit
Default Internal Set Point for Skip Cycle Operation and Standby Detection
Default Internal Set Point to Leave Standby
Propagation Delay from CS Detected to Gate Turned Off (Pin 5 Loaded by 1.0 nF)
Leading Edge Blanking Duration
Internal Oscillator
Oscillation Frequency, 65 kHz version (V
fb
= 2.5 V)
Oscillation Frequency, 100 kHz version (V
fb
= 2.5 V)
Oscillation Frequency, 133 kHz version (V
fb
= 2.5 V)
Internal Modulation Swing, in Percentage of Fsw) (Typical) (Note 4)
Internal Swing Period with a 82 nF Capacitor to Pin 7) (Typical) (Note 4)
Maximum Duty−Cycle
Typical Soft−Start Period with a 82 nF to Pin 7 (Note 4)
SS Charging/Discharging Current
Timer Charging Current (Typical) (Note 4)
Timer Peak Voltage
Timer Valley Voltage
Feedback Section
(V
CC
= 13 V)
Opto Current Source (V
fb
= 0.75 V)
Pin 3 to Current Setpoint Division Ratio (Note 3)
−
−
−
−
−
−
7
7
7
7
7
56
88
118
−
−
75
−
35
−
3.5
1.9
65
100
133
±4.0
5.0
80
5.0
60
1.36
4.0
2.2
69
108
140
−
−
85
−
75
−
4.5
2.6
kHz
kHz
kHz
%
ms
%
ms
mA
mA
V
V
−
I
ratio
2
−
190
−
235
3.0
270
−
mA
−
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5
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