Can be used in designs presently using the SYM20C15
Single-chip, half-duplex 1200 bits per second FSK modem
Bell 202 shift frequencies of 1200Hz and 2200Hz
3.3V - 5.0V power supply
Transmit-signal wave shaping
Receive band-pass filter
Low power: optimal for intrinsically safe applications
CMOS compatible
Internal oscillator requires 460.8kHz crystal or ceramic resonator
Meets HART physical layer requirements
Industrial temperature range of -40°C to +85°C
Available in 28-pin PLCC and 32-pin LQFP packages
Data Sheet
2.0 Description
The A5191HRT is a single-chip, CMOS modem for use in highway addressable remote transducer (HART) field instruments and masters. The modem and
a few external passive components provide all of the functions needed to satisfy HART physical layer requirements including modulation, demodulation,
receive filtering, carrier detect, and transmit-signal shaping. The A5191HRT is pin-compatible with the SYM20C15. See the Pin Description and Functional
Description sections for details on pin compatibility with the SYM20C15.
The A5191HRT uses phase continuous frequency shift keying (FSK) at 1200 bits per second. To conserve power the receive circuits are disabled during
transmit operations and vice versa. This provides the half-duplex operation used in HART communications.
Analog input sets the dc operating point of the operational amplifiers and comparators and is usually selected to split the
dc potential between V
DD
and V
SS
. See IAREF in DC Characteristics, Table 6
Analog input controls at which level the carrier detect (OCD) becomes active. This is determined by the dc voltage
difference between ICDREF and IAREF. Selecting ICDREF - IAREF equal to 0.08 V
DC
will set the carrier detect to a nominal
100 mV
p-p
When at logic low (V
SS
) this input holds all the digital logic in reset. During normal operation INRESET should be at V
DD
.
INRESET should be held low for a minimum of 10nS after V
DD
= 2.5V as shown in Figure 3
Active-low input selects the operation of the modulator. OTXA is enabled when this signal is low. This signal must be
held high during power-up
Input accepts the 1200/2200Hz signals from the external filter
Positive input of the carrier detect comparator and the receiver filter comparator
Input to the modulator accepts digital data in NRZ form. When ITXD is low, the modulator output frequency is 2200Hz.
When ITXD is high, the modulator output frequency is 1200Hz.
Input to the internal oscillator must be connected to a parallel mode 460.8kHz ceramic resonator when using the internal
oscillator or grounded when using an external 460.8kHz clock signal
The current through this output controls the operating parameters of the internal operational amplifiers and
comparators. For normal operation, OCBIAS current is set to 2.54A.
Output goes high when a valid input is recognized on IRXA. If the received signal is greater than the threshold specified
on ICDREF for four cycles of the IRXA signal, the valid input is recognized.
Signal is the square wave output of the receiver high-pass filter
Signal outputs the digital receive data. When the received signal (IRXA) is 1200Hz, ORXD outputs logic high. When the
received signal (IRXA) is 2200Hz, ORXD outputs logic low. ORXD is qualified internally with OCD.
Output provides the trapezoidal signal controlled by ITXD. When ITXD is low, the output frequency is 2200Hz. When
ITXD is high, the output frequency is 1200Hz. This output is active when INRTS is low and 0.5 V
DC
when INRTS is high.
Output from the internal oscillator must be connected to an external 460.8kHz clock signal or to a parallel mode
460.8kHz ceramic resonator when using the internal oscillator
Factory test pins; for normal operation, tie these signals as per Table 1 and Table 2
Power for the digital modem circuitry
Power for the analog modem circuitry
Analog and digital ground
ICDREF
Carrier Detect Reference Voltage
INRESET
INRTS
IRXA
IRXAC
ITXD
IXTL
OCBIAS
OCD
ORXAF
ORXD
OTXA
OXTL
Reset Digital Logic
Request to Send
Analog Receive Input
Analog Receive Comparator Input
Digital Transmit Input (CMOS)
Oscillator Input
Comparator Bias Current
Carrier Detect Output
Analog Receive Filter Output
Digital Receive Output (CMOS)
Analog Transmit Output
Oscillator Output
TEST(12:1) Factory Test
VDD
VDDA
VSS
VSSA
Digital Power
Analog Supply Voltage
Ground
Analog Ground
Figure 3: Reset Timing
Note:
This signal is also present on the LSI 20C15. It is labeled as Test6. The 20C15 data sheet mentions the reset function of this pin but does not emphasize its use to reset the chip. Reliable operation
of the modem requires a hardware reset as shown in Figure 3. This is true for the AMIS 12197-503 and 12197-504 as well as the LSI 20C15.
AMI Semiconductor - Rev. 2.0, Mar. 05
www.amis.com
3
A5191HRT AMIS HART™ Modem
4.0 Functional Description
Data Sheet
The A5191HRT is a functional equivalent of the SYM20C15 HART Modem. It contains a transmit data modulator and signal shaper, carrier detect circuitry,
analog receiver and demodulator circuitry and an oscillator, as shown in Figure 4.
The internal HART modem modulates the transmit-signal and demodulates the receive signal. The transmit-signal shaper enables the A5191HRT to transmit
a HART compliant signal. The carrier is detected by comparing the receiver filter output with the difference between two external voltage references. The
analog receive circuitry band-pass filters the received signal for input to the modem and the carrier detect circuitry. The oscillator provides the modem
with a stable time base using either a simple external resonator or an external clock source.
Figure 4: A5191HRT Block Diagram
4.1 A5191HRT Logic
The modem consists of a modulator and demodulator. The modem uses shift frequencies of nominally 1200Hz (for a 1) and 220Hz (for a 0). The bit rate
is 1200 bits/second.
4.1.1 Modulator
The modulator accepts digital data in NRZ form at the ITXD input and generates the FSK modulated signal at the OTXA output. INRTS must be a logic
low for the modulator to be active.
4.1.2 Demodulator
The demodulator accepts an FSK signal at the IRXA input and reproduces the original modulating signal at the ORXD output. The nominal bit rate is 1200
bits per second. Figure 5 illustrates the demodulation process.
Figure 5: Demodulator Signal Timing
AMI Semiconductor - Rev. 2.0, Mar. 05
www.amis.com
4
A5191HRT AMIS HART™ Modem
Data Sheet
The output of the demodulator is qualified with the carrier detect signal (OCD), therefore, only IRXA signals large enough to be detected (100mV
p-p
typically) by the carrier detect circuit produce received serial data at ORXD.
Maximum demodulator jitter is 12 percent of one bit given input frequencies within HART specifications, a clock frequency of 460.8kHz (±1.0 percent)
and zero input (IRXA) asymmetry.
4.2 Transmit-Signal Shaper
The transmit-signal shaper generates a HART compliant FSK modulated signal at OTXA. Figure 6 and Figure 7 show the transmit-signal forms of the
A5191HRT.
For IAREF = 1.235 V
DC
, OTXA will have a voltage swing from approximately 0.25 to 0.75 V
DC
.
Figure 6: OTXA Waveform (1200Hz)
Figure 7: OTXA Waveform (2200Hz)
4.3 Carrier Detect Circuitry
The carrier detect comparator shown in Figure 8 generates logic low output if the IRXAC voltage is below ICDREF. The comparator output is fed into a
carrier detect block (see Figure 4). The carrier detect block drives the carrier detect output pin OCD high if INRTS is high and four consecutive pulses out
of the comparator have arrived. OCD stays high as long as INRTS is high and the next comparator pulse is received in less than 2.5ms. Once OCD goes
inactive, it takes four consecutive pulses out of the comparator to assert OCD again. Four consecutive pulses amount to 3.33ms when the received signal
is 1200Hz and to 1.82ms when the received signal is 2200HZ.
4.4 Analog Receiver Circuitry
4.4.1 Voltage References
The A5191HRT requires two voltage references, IAREF and ICDREF.
IAREF sets the dc operating point of the internal operational amplifiers and comparators. A 1.235 V
DC
reference (Analog Devices AD589) is suitable as
IAREF.
The level at which OCD (carrier detect) becomes active is determined by the dc voltage difference (ICDREF - IAREF). Selecting a voltage difference of 0.08
stm32/stm8
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