NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
February 2000
NM24C02/03 – 2K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The NM24C02/03 devices are 2048 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 1Kbit) of the memory of the NM24C03 can be
write protected by connecting the WP pin to V
CC
. This section of
memory then becomes unalterable unless WP is switched to V
SS
.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Features
I
Extended operating voltage 2.7V – 5.5V
I
400 KHz clock frequency (F) at 2.7V - 5.5V
I
200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I
IIC compatible interface
– Provides bi-directional data transfer protocol
I
Schmitt trigger inputs
I
Sixteen byte page write mode
– Minimizes total write time per byte
I
Self timed write cycle
Typical write cycle time of 6ms
I
Hardware Write Protect for upper half (NM24C03 only)
I
Endurance: 1,000,000 data changes
I
Data retention greater than 40 years
I
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I
Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
H.V. GENERATION
TIMING &CONTROL
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
E2PROM
ARRAY
SDA
SCL
XDEC
A2
A1
A0
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
DS500069-1
© 1998 Fairchild Semiconductor Corporation
NM24C02/03 Rev. G
1
www.fairchildsemi.com
NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 seconds)
ESD Rating
–65°C to +150°C
6.5V to –0.3V
+300°C
2000V min.
Operating Conditions
Ambient Operating Temperature
NM24C02/03
NM24C02E/03E
NM24C02V/03V
Positive Power Supply
NM24C02/03
NM24C02L/03L
NM24C02LZ/03LZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
DC Electrical Characteristics (2.7V to 5.5V)
Symbol
Parameter
Test Conditions
Min
I
CCA
I
SB
Active Power Supply Current
Standby Current
f
SCL
= 400 KHz
f
SCL
= 100 KHz
V
IN
= GND
or V
CC
V
CC
= 2.7V - 5.5V
V
CC
= 2.7V - 5.5V (L)
V
CC
= 2.7V - 4.5V (LZ)
Limits
Typ
(Note 1)
0.2
10
1
0.1
0.1
0.1
Units
Max
1.0
50
10
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
mA
µA
µA
µA
µA
µA
V
V
V
I
LI
I
LO
V
IL
V
IH
V
OL
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
–0.3
V
CC
x 0.7
I
OL
= 3 mA
Capacitance
T
A
= +25°C, f = 100/400 KHz, V
CC
= 5V
(Note 2)
Symbol
C
I/O
C
IN
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
Note 1:
Typical values are T
A
= 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.
Note 2:
This parameter is periodically sampled and not 100% tested.
4
NM24C02/03 Rev. G
www.fairchildsemi.com
NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10 ns
V
CC
x 0.3 to V
CC
x 0.7
1 TTL Gate and C
L
= 100 pF
AC Testing Input/Output Waveforms
0.9V
CC
0.1V
CC
0.7V
CC
0.3V
CC
DS500069-4
Read and Write Cycle Limits (Standard and Low V
CC
Range 2.7V - 5.5V)
Symbol
f
SCL
T
I
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time - NM24C02/03
- NM24C02/03L, NM24C02/03LZ
100 KHz
Min
Max
100
100
0.3
4.7
4.0
4.7
4.0
4.7
20
250
1
300
4.7
300
10
15
3.5
400 KHz
Min
Max
400
50
0.1
1.3
0.6
1.5
0.6
0.6
20
100
0.3
300
0.6
50
10
15
0.9
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 3)
Note 3:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C02/03 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
tF
tHIGH
tLOW
SCL
tLOW
tR
SDA
IN
SDA
OUT
;;
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tDH
tAA
DS500069-5
5
NM24C02/03 Rev. G
www.fairchildsemi.com
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