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NM27C256V120

产品描述262,144-Bit (32K x 8) High Performance CMOS EPROM
产品类别存储    存储   
文件大小82KB,共11页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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NM27C256V120概述

262,144-Bit (32K x 8) High Performance CMOS EPROM

NM27C256V120规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Fairchild
零件包装代码QFJ
包装说明QCCJ, LDCC32,.5X.6
针数32
Reach Compliance Codeunknow
ECCN代码EAR99
最长访问时间120 ns
I/O 类型COMMON
JESD-30 代码R-PQCC-J32
JESD-609代码e0
长度13.995 mm
内存密度262144 bi
内存集成电路类型OTP ROM
内存宽度8
功能数量1
端子数量32
字数32768 words
字数代码32000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织32KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC32,.5X.6
封装形状RECTANGULAR
封装形式CHIP CARRIER
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
编程电压12.75 V
认证状态Not Qualified
座面最大高度3.56 mm
最大待机电流0.0001 A
最大压摆率0.035 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度11.455 mm

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NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
July 1998
NM27C256
262,144-Bit (32K x 8) High Performance CMOS EPROM
General Description
The NM27C256 is a 256K Electrically Programmable Read Only
Memory. It is manufactured in Fairchild’s latest CMOS split gate
EPROM technology which enables it to operate at speeds as fast
as 90 ns access time over the full operating range.
The NM27C256 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 90 ns access time provides high speed
operation with high-performance CPUs. The NM27C256 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The NM27C256 is configured in the standard EPROM pinout
which provides an easy upgrade path for systems which are
currently using standard EPROMs.
The NM27C256 is one member of a high density EPROM Family
which range in densities up to 4 Mb.
Features
s
High performance CMOS
— 90 ns access time
s
JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
s
Drop-in replacement for 27C256 or 27256
s
Manufacturer’s identification code
Block Diagram
VCC
GND
VPP
OE
Output Enable
and Chip Enable Logic
CE/PGM
Data Outputs O0 - O7
Output
Buffers
Y Decoder
..
Y Gating
A0 - A14
Address
Inputs
.......
X Decoder
DS010833-1
© 1998 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com

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