NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Connection Diagrams
27C080 27C040 27C020 27C010 27C256
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
XX/
VPP
XX/
VPP
XX/
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
DIP
NM27C512
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE/PGM
O7
O6
O5
O4
O3
27C256 27C010 27C020 27C040 27C080
VCC
VCC
A14
A13
A8
A9
A11
OE
A10
CE/PGM
O7
O6
O5
O4
O3
VCC
VCC
A18
A17
A14
A13
A8
A9
A11
OE
A10
O7
O6
O5
O4
O3
VCC
A18
A17
A14
A13
A8
A9
A11
OE/
VPP
A10
O7
O6
O5
O4
O3
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
XX/PGM XX/PGM
XX
A17
A14
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
CE/PGM CE/PGM
DS010834-2
Compatible EPROM pin configurations are shown in the blocks adjacement to the NM27C512 pins.
Commercial Temp Range (0
°
C to +70
°
C)
Parameter/Order Number
NM27C512 Q, N, V 90
NM27C512 Q, N, V 120
NM27C512 Q, N, V 150
Pin Names
A0–A15
CE/PGM
OE
O0–O7
NC
Addresses
Chip Enable/Program
Output Enable
Outputs
Don’t Care (During Read)
Access Time (ns)
90
120
150
Industrial Temp Range (-40
°
C to +85
°
C)
Parameter/Order Number
NM27C512 QE, NE, VE 120
NM27C512 QE, NE, VE 150
Q = Quartz-Windowed Ceramic DIP Package
N = Plastic DIP Package
V = PLCC Package
• All packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower speeds.
PLCC
A7
A12
A15
NC
VCC
A14
A13
4
3
2
1 32 31 30
Access Time (ns)
120
150
A6
A5
A4
A3
A2
A1
A0
NC
O0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
A8
A9
A11
NC
OE/VPP
A10
CE/PGM
O7
O8
O1
O2
GND
NC
O3
O4
O5
DS010834-3
2
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages Except A9 with
Respect to Ground
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
-65°C to +150°C
ESD Protection
(MIL Std. 883, Method 3015.2)
All Output Voltages with
Respect to Ground
>2000V
V
CC
+ 1.0V to GND -0.6V
-0.6V to +7V
-0.7V to +14V
-0.6V to +7V
Operating Range
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
+5V
+5V
Tolerance
±10%
±10%
Read Operation
DC Electrical Characteristics
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC1
I
CC2
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current (CMOS)
V
CC
Standby Current
V
CC
Active Current
V
CC
Active Current
CMOS Inputs
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.5
2.0
Max
0.8
V
CC
+1
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -2.5 mA
CE = V
CC
±0.3V
CE = V
IH
CE = OE = V
IL
f = 5 MHz
3.5
100
1
40
35
10
V
CC
- 0.7
V
CC
1
10
µA
mA
mA
mA
µA
V
µA
µA
CE = GND, f = 5 MHz
Inputs = V
CC
or GND, I/O = 0 mA
C, E Temp Ranges
V
PP
= V
CC
I
PP
V
PP
I
LI
I
LO
V
IN
= 5.5V or GND
V
OUT
= 5.5V or GND
-1
-10
AC Electrical Characteristics
Symbol
t
ACC
t
CE
t
OE
t
DF
t
OH
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to
Output Float
Output Hold from Addresses, CE or OE,
Whichever Occurred First
0
90
Max
90
90
40
35
120
Min
Max
120
120
50
25
0
150
Min
Max
150
150
50
45
0
Units
ns
3
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Capacitance
T
A
= +25°C, f = 1 MHz (Note 2)
Symbol
C
IN1
C
OUT
C
IN2
Parameter
Input Capacitance
except OE/V
PP
Output Capacitance
OE/V
PP
Input
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ
6
9
20
Max
12
12
25
Units
pF
pF
pF
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level (Note 9)
Inputs
Outputs
AC Waveforms
(Notes 6, 7)
ADDRESS
2V
0.8V
Address Valid
CE
2V
0.8V
t
CF
(Note 4, 5)
OE
2V
0.8V
t
CE
t
OE
(Note 3)
t
DF
(Note 4, 5)
Valid Output
OUTPUT
2V
0.8V
Hi-Z
t
ACC
(Note 3)
Hi-Z
t
OH
DS010834-4
Note 1:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
–t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 9:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
4
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Programming Characteristics
(Note 10) and (Note 11)
Symbol
t
AS
t
OES
t
DS
t
VCS
t
AH
t
DH
t
CF
t
PW
t
OEH
t
DV
t
PRT
t
VR
I
PP
I
CC
T
R
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Parameter
Address Setup Time
OE Setup Time
Data Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Chip Enable to Output Float Delay
Program Pulse Width
OE Hold Time
Data Valid from CE
OE Pulse Rise Time
during Programming
V
PP
Recovery Time
V
PP
Supply Current during
Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
Min
1
1
1
1
0
1
Typ
Max
Units
µs
µs
µs
µs
µs
µs
OE = V
IL
0
45
1
50
60
105
ns
µs
µs
OE = V
IL
50
1
CE = V
IL
OE = V
PP
250
ns
ns
µs
30
50
20
6.25
12.5
5
0
2.4
0.8
0.8
4
2
2
0.45
25
6.5
12.75
30
6.75
13
mA
mA
°C
V
V
ns
V
V
V
V
Programming Waveforms
Program
Addresses
2.0V
0.8V
t AS
2.0V
Data
0.8V
t DS
12.75V
0.8V
tPRT
CE/PGM
t OES
t VPS
t VCS
6.25V
t OEH
t VR
Data In Stable
ADD N
t DH
Hi-Z
2.0V
0.8V
t DV
Data Out Valid
ADD N
t CF
t AH
Address N
Program Verify
OE/VPP
t PW
VCC
DS010834-5
Note 10:
Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 11:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 12:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µF
capacitor is required across V
CC
to GND to suppress spurious voltage transients which
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