Memory revolutionizes the design of high performance and durable
mass storage memory systems for the Industrial Avionics and Military markets With its innovative features
like low power blocked architecture high read write performance and expanded temperature range any
design or mission is free from the dependence on battery backed up memory or highly sensitive and slow
rotating media drives
Using the VE28F008 in a PCMCIA 2 1 Flash Memory card ATA drive or any size or shape module will allow
data application or operating systems to be updated or collected anywhere and at anytime This data on
demand feature ensures protection from obsolesce through field or in system software updates
The VE28F008’s highly integrated Command User Interface and Write State Machine decreases the size and
complexity of system software while providing high read write and erase performance The sixteen separately
erasable 64 Kbyte blocks along with a multiple write data protection system provides assurance that highly
important data will be available when needed
The VE28F008 is offered in a 40-lead TSOP (Thin Small Outline Package) which is capable of performing in
temperatures from
b
40 C to
a
125 C It employs advanced CMOS circuitry for systems requiring low power
consumption and noise immunity The VE28F008’s 95 ns access time provides superior performance when
compared to magnetic mass storage
Manufactured on Intel’s 0 8 micron ETOX
TM
III process the VE28F008 provides the highest levels of quality
reliability and cost effectiveness
Microsoft is a trademark of Microsoft Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
May 1994
Order Number 271305-001
VE28F008
The
Status Register
indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation
The
RY BY
output gives an additional indicator of
WSM activity providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase
for example) Status polling using RY BY minimizes
both CPU overhead and system power consump-
tion When low RY BY indicates that the WSM is
performing a block erase or byte write operation
RY BY high indicates that the WSM is ready for new
commands block erase is suspended or the device
is in deep powerdown mode
Maximum access time is
95 ns (t
ACC
)
over the avi-
onics temperature range (
b
40 C to
a
125 C) and
over V
CC
supply voltage range 4 75V to 5 25V
I
CC
active current
(CMOS Read) is
35 mA maximum
at 8 MHz
When the CE and RP pins are at V
CC
the
I
CC
CMOS
Standby
mode is enabled
A
Deep Powerdown
mode is enabled when the RP
pin is at GND minimizing power consumption and
providing write protection Reset time of 400 ns is
required from RP switching high until outputs are val-
id to read attempts Equivalently the device has a
wake time of 1
ms
from RP high until writes to the
Command User Interface are recognized by the
VE28F008 With RP at GND the WSM is reset and
the Status Register is cleared
PRODUCT OVERVIEW
The VE28F008 is a high-performance
8 Mbit
(8 388 608 bit) memory organized as
1 Mbyte
(1 048 576 bytes) of 8 bits each
Sixteen 64 Kbyte
(65 536 byte)
blocks
are included on the VE28F008
A memory map is shown in Figure 4 of this specifica-
tion A block erase operation erases one of the six-
teen blocks of memory in typically
1 6 seconds
in-
dependent of the remaining blocks Each block can
be independently erased and written
10 000 cycles
Erase Suspend
mode allows system software to
suspend block erase to read data or execute code
from any other block of the VE28F008
The VE28F008 is available in a
40-lead TSOP
pack-
age Pinout is shown in Figure 2 of this specification
The
Command User Interface
serves as the inter-
face between the microprocessor or microcontroller
and the internal operation of the VE28F008
Byte Write and Block Erase Automation
allow
byte write and block erase operations to be execut-
ed using a two-write command sequence to the
Command User Interface The internal
Write State
Machine
(WSM) automatically executes the algo-
rithms and timings necessary for byte write and
block erase operations including verifications
thereby unburdening the microprocessor or micro-
controller Writing of memory data is performed in
byte increments typically within
9
ms
an 80% im-
provement over current flash memory products
I
PP
byte write and block erase currents
are
30 mA
maximum V
PP
byte write and block erase volt-
age
is
11 4V to 12 6V
2
VE28F008
271305 –1
Figure 1 Block Diagram
Table 1 Pin Description
Symbol
A
0
–A
19
DQ
0
–DQ
7
Type
INPUT
INPUT OUTPUT
Name and Function
ADDRESS INPUTS
for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUTS
Inputs data and commands during Command
User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle
CHIP ENABLE
Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high deselects the
memory device and reduces power consumption to standby levels
RESET DEEP POWERDOWN
Puts the device in the deep powerdown
mode RP is active low RP high gates normal operation RP also locks
out block erase or byte write operations when active low providing data
protection during power transitions RP active resets internal
automation Exit from Deep Powerdown sets device to read-array mode
OUTPUT ENABLE
Gates the device’s outputs through the data buffers
during a read cycle OE is active low
WRITE ENABLE
Controls writes to the Command User Interface and
array blocks WE is active low Addresses and data are latched on the
rising edge of the WE pulse
CE
INPUT
RP
INPUT
OE
WE
INPUT
INPUT
3
VE28F008
Table 1 Pin Description
(Continued)
Symbol
RY BY
Type
OUTPUT
Name and Function
READY BUSY
Indicates the status of the internal Write State Machine When
low it indicates that the WSM is performing a block erase or byte write operation
RY BY high indicates that the WSM is ready for new commands block erase is
suspended or the device is in deep powerdown mode RY BY is always active and
does
NOT
float to tri-state off when the chip is deselected or data outputs are
disabled
BLOCK ERASE BYTE WRITE POWER SUPPLY
for erasing blocks of the array
or writing bytes of each block
NOTE
k
V
PPLMAX
memory contents cannot be altered
With V
PP
DEVICE POWER SUPPLY (5V
g
5%)
GROUND
V
PP
V
CC
GND
271305 –2
Figure 2 TSOP Pinout
4
VE28F008
271305 –3
Figure 3 VE28F008 Array Interface to Intel386
TM
SL Microprocessor Superset through PI Bus
(Including RY BY Masking and Selective Powerdown) for DRAM Backup during System SUSPEND
Resident O S and Applications and Motherboard Solid-State Disk
PRINCIPLES OF OPERATION
The VE28F008 includes on-chip write automation to
manage write and erase functions The Write State
Machine allows for 100% TTL-level control inputs
fixed power supplies during block erasure and byte
write and minimal processor overhead with RAM-
like interface timings
After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
VE28F008 functions as a read-only memory Manip-
ulation of external memory-control pins allow array
read standby and output disable operations Both
Status Register and intelligent identifier can
also be accessed through the Command User Inter-
face when V
PP
e
V
PPL
This same subset of operations is also available
when high voltage is applied to the V
PP
pin In addi-
tion high voltage on V
PP
enables successful block
erasure and byte writing of the device All functions
associated with altering memory contents byte
write block erase status and intelligent identifier
are accessed via the Command User Interface and
verified thru the Status Register
Commands are written using standard microproces-
sor write timings Command User Interface contents
serve as input to the WSM which controls the block
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