STM-4/STM-1/E4
3.3 V Multifunction
Transmitter and
Receiver
GD16591/GD16592
Preliminary
General Description
The GD16591 and GD16592 is a front-
end transmitter/receiver chip set de-
signed for multiple line interfaces:
u
STM-4 / OC-12
u
STM-1 / OC-3
u
PDH E4
This chip set is designed to interconnect
the high speed line interface to standard
CMOS ASICs providing low speed data
interface.
The GD16591/592 devices are designed
for use in both electrical and optical line
interface modules. The devices support
line speeds of:
u
140/155 Mbit/s NRZ mode for E4/
OC-3/STM-1 for an optical line inter-
face.
u
280/311 Mbit/s for E4/OC-3/STM-1 in
CMI mode for electrical line interface,
where en-/decoding is made at the
system site.
u
622 Mbit/s NRZ mode line speed for
OC-12/STM-4 operation.
The on-chip VCO and PLL blocks for
clock generation eliminate the need for
an external high-speed clock signal.
The GD16592 comprises a Limiting Input
Amplifier (LIA), Clock & Data Recovery,
and a configurable DeMUX circuit. The
LIA offers a differential input sensitivity of
10 mV peak to peak for the high-speed
serial input. A Lock Detect output moni-
tors the PLL locked onto the received se-
rial data.
The low-speed interface I/O´s are
LVTTL- level, and the high-speed I/O´s
are differential LVPECL levels (The LIA
input is usable as LVPECL input).
System (local) Loop-back and Line (re-
mote) Loop-back functions offer simpli-
fied manufacturing and field testing.
Low power consumption is achieved by
the 3.3 V single power supply and by
omitting all circuitry, which can easily be
implemented in the low speed system
ASIC, thus reducing the overall power
consumption.
The devices are housed in 48 pin
EDQUAD TQFP™ plastic packages.
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Features
General
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Low jitter on-chip VCO and PLL.
Jitter performance exceeds the rec-
ommendations of ITU-T and Bellcore.
The chip set offers seven line and
system speed mode:
622 Mbit/s
↔
78 Mbit/s, 8 bit
311 Mbit/s
↔
78 Mbit/s, 4 bit
155 Mbit/s
↔
78 Mbit/s, 2 bit
155 Mbit/s
↔
19 Mbit/s, 8 bit
280 Mbit/s
↔
70 Mbit/s, 4 bit
140 Mbit/s
↔
70 Mbit/s, 2 bit
140 Mbit/s
↔
17 Mbit/s, 8 bit
Four phase selectable clock to data
timing at parallel interface.
Selectable reference clock input fre-
quencies:
17.408/19.44MHz, 34.816/
38.88MHz, and 69.632/77.76MHz.
Loop Back for System & Line test
modes.
48 pin EDQUAD TQFP™ packages.
Single supply: 3.1 ... 3.6 V.
GD16591 (Transmitter)
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CMOS System ASIC
Data
70/78 Mbit/s
17/19 Mbit/s
2 / 4 / 8 bit
Clock
GD16591
MUX/
Retiming PLL
Line Interface
140/155 Mbit/s (optical)
280/311 Mbit/s (electrical)
622 Mbit/s (STM-4 opt.)
8:1 / 4:1 / 2:1 MUX.
Differential transmitted clock output.
LVPECL data outputs.
Optional forward/counter clocking
scheme.
Power dissipation, typ.: 350 mW
GD16592 (Receiver)
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System / Line Loop Back
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1:8 / 1:4 / 1:2 DeMUX.
Clock and Data Recovery:
Bang-Bang phase detector between
VCO clock and data.
LIA: serial differential input voltage
range 10 ... 1400 mV
PP
.
Power dissipation, typ.: 450 mW
Data
70/78 Mbit/s
17/19 Mbit/s
2 / 4 / 8 bit
Clock
Line Interface
140/155 Mbit/s (optical)
280/311 Mbit/s (electrical)
622 Mbit/s (STM-4 opt.)
Applications
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Data Sheet Rev. 09
GD16592
DeMUX/
CDR with PLL
Tele Communication systems:
– SDH/SONET
– PDH
– ATM over SDH/SONET
Functional Details
General
The Transmitter and Receiver functional
blocks are split up into two devices in or-
der to reduce cross talk and pin count
per device.
The telecommunication system (line
speed group) is choosen by the select
pin (SELPDH):
u
For SDH/SONET (622/311/155 Mbit/s)
set SELPDH High.
u
For PDH (280/140 Mbit/s)
set SELPDH Low.
The devices can operate in different line
and system speed modes; selected by
DSEL1, DSEL2 and SELPDH,
see Table 1.
The bit order on the low speed parallel
interface is defined with bit 0 as the first
bit transferred (ID0 for the transmitter
and OD0 for the receiver).
The bit rate per connection can be kept
at 78(70) Mbit/s regardless of the line
speed. In addition a separate low speed
1:8 mode support the transmission of
155(140) Mbit/s serial to 19(17) Mbit/s,
8 bit parallel. All data pins are used.
Both devices have a selectable clock di-
vider for the system reference clock,
which allows the circuits to be driven
from either 19 (17), 38(35), or
78(70) MHz reference, independantly of
the line and system speed. The refer-
ence clock frequency is selected by
RSEL1, RSEL2, and SELPDH,
see table 2.
Connecting the differential Line Loop Sig-
nals and Clocks (LLxxx) between
GD16591 and GD16592 allows clock re-
covered loop-back of the received line
signal, when LLB on both devices is low.
Connecting the differential System Loop
Signals (SLSxx) between GD16591 and
GD16592 allows system loop-back, when
SLB on both devices is low.
Both circuits comprise fully integrated
PLL functions for re-timing data at the
transmit site, and for clock and data re-
covery at the receive site.
A passive loop filter (consisting of a re-
sistor and a capacitor) is used for both
devices. The external loop filter connect-
ing OUCHP to VCTL is shown in
Figure 1
(for the transmitter GD16591)
and
Figure 2
(for the receiver GD16592).
The loop filter values are optimized at the
evaluation board GD90591/592.
The optimal values depends on the ac-
tual application. The suggested values in
Figures 1
and
2
can be used as starting
point for the optimization.
VCTL
VCCA
OUCHP
1kΩ 1
µ
F
VCTL
VCCA
OUCHP
22Ω 1
µ
F
Figure 1.
Loop Filter for the Transmitter,
GD16591.
Figure 2.
Loop Filter for the Receiver,
GD16592.
SELPDH
0
0
0
0
1
1
1
1
Table 1.
DSEL1
0
0
1
1
0
0
1
1
DSEL2
0
1
0
1
0
1
0
1
Line Speed
140 Mbit/s
140 Mbit/s
280 Mbit/s
---
155 Mbit/s
155 Mbit/s
311 Mbit/s
622 Mbit/s
System Speed
70 Mbit/s
17 Mbit/s
70 Mbit/s
---
78 Mbit/s
19 Mbit/s
78 Mbit/s
78 Mbit/s
Used Bits
0&1
0...7
0...3
---
0&1
0...7
0...3
0...7
Line and system speed mode selection.
SELPDH
0
0
0
1
1
1
Table 2.
RSEL1
0
1
1
0
1
1
RSEL2
0/1
0
1
0/1
0
1
Ref. Clock
69.632 MHz
34.816 MHz
17.408 MHz
77.76 MHz
38.88 MHz
19.44 MHz
Reference clock frequency selection.
Data Sheet Rev. 09
GD16591/GD16592
Page 2 of 16
The Transmitter - GD16591
The schematic block diagram of
GD16591 is shown in
Figure 3.
By the select signal (CSEL) two different
reference clock inputs can be selected
(CKR0/CKR1). This allows for line timing
in normal operation with a selection of a
separate reference when the received
line input data is flawed. Thus, allowing
forwarding alarm status in the event of a
loss of received data.
DSEL1
DSEL2
PSEL1
PSEL2
LLCIN
LLCIP
LLSIP
LLSIN
LLB
SLB
SLSOP
SLSON
Forward Clocking
Co-directional timing for input data is pro-
vided. The phase can with the select pins
PSEL1-2 be set to 0°/ 90°/ 180°/ 270° dif-
ference between data input sampling and
reference clock (CKR0/CKR1).
When forward clocking, the frequency of
the reference clock must be identical to
the input data bit rate.
I.e. for 78(70) Mbit/s use 78(70) MHz ref-
erence clock, and for 19(17) Mbit/s use
19(17) MHz reference clock. Refer to AC
Characteristics on
page 12.
ID0
ID7
MUX
LD
SOP
SON
SELPDH
VCTL
SELTCK
VCO
Clock
Gen.
0 /90
180
o
/270
o
o
o
Phase
Adjust
COP
CON
CKOUT
Divide
by
1/2/4
V
R
U
D
U
D
RSEL1
RSEL2
VCC
VCCA
CKR0
CKR1
CSEL
PFC
GND
GNDA
Counter Clocking
In addition, contra directional timing is
provided. The phase between input and
CKOUT is adjustable with (0°/90°/180°/
270°). Refer to AC Characteristics on
page 12.
CKOUT is kept synchronous to the refer-
ence clock by the Phase Frequency
Comparator (PFC).
OUCHP
Figure 3.
The GD16591 Multifunction Transmitter.
Output
LVPECL
100nF
Input
LVPECL
100nF
Outputs
The outputs from the multiplexer is fed to
differential LVPECL output stages. See
Figures 4
and
5
for output temination.
The serial data output (SOP/SON) are
accompanied by a serial clock output
(COP/CON). See timing data on
page 12.
SLSOP/SLSON is enabled when SLB is
low. When SLB is high (e.g. by internal
pull-up resistor) SLSOP = 0 and
SLSON = 1; thus avoiding noise injection
at normal operation.
180Ω
0V
(GND)
180Ω
50Ω
50Ω
2V
(VCC -1.3V)
Figure 4.
LVPECL Output Termination, AC-coupled.
Output
LVPECL
Input
LVPECL
50Ω
50Ω
1.3V
(VCC -2V)
Figure 5.
LVPECL Output Termination, DC-coupled.
Data Sheet Rev. 09
GD16591/GD16592
Page 3 of 16
The Receiver - GD16592
The schematic block diagram of
GD16592 is shown in
Figure 6.
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in
CDR mode
as a true digital type de-
tector, producing a binary output. It sam-
ples the incoming data twice each bit
period: once in the transition of the (pre-
vious) bit period and once in the middle
of the bit period. When a transition oc-
curs between 2 consecutive bits - the
value of the sample in the transition be-
tween the bits will show whether the
VCO clock leads or lags the data. Hence
the PLL is controlled by the bit transition
point, thereby ensuring that data is sam-
pled in the middle of the eye, once the
system is in CDR mode. The external
loop filter components control the chara-
cteristics of the PLL.
The binary output of either the PFC or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is fed to a charge pump capable of
sinking or sourcing current or tristating.
The output of the charge pump is filtered
through the loop filter and controls the
tuning-voltage of the VCO.
As a result of the continuous monitoring
lock-detect circuit the VCO frequency
never deviates more than 500 ppm
(2000 ppm) from the reference clock be-
fore the PLL is considered to be ’Out of
Lock’. Hence the acquisition time is pre-
dictable and short and the output clock
CKOUT is always kept within the
500 ppm (2000 ppm) limits, ensuring
safe clocking of down stream circuitry.
Lock Detect Circuit
The lock detect circuit continuously moni-
tors the frequency difference between
the reference clock and the divided VCO
clock. If the reference clock and the di-
vided VCO frequency differs by more
than 500 ppm (or 2000 ppm, selectable),
it switches the PFC into the PLL in order
to pull the VCO back inside the lock-in
range. This mode is called
the acquisi-
tion mode.
The PFC is used to ensure predictable
lock up conditions for the GD16592 by
locking the VCO to an external reference
clock source. It is only used during acqui-
sition and pulls the VCO into the lock
range where the Bang-Bang phase de-
tector is capable of acquiring lock to in-
coming data. The PFC is made with
digital set/reset cells giving it a true
phase and frequency characteristic.
Once the VCO is inside the lock-range
the lock-detection circuit switches the
Bang-Bang phase detector into the PLL
in order to lock to the data signal. This
mode is called
CDR mode.
The LOCK Signal
The status of the lock-detection circuit is
given by the LOCK signal. In CDR mode
LOCK is steady high. In acquisition mode
LOCK is alternating indicating the con-
tinuous shifts between the Bang-Bang
Detector (high) and the PFC (low).
The LOCK output may be used to gener-
ate a pseudo
Loss Of Signal
(LOS). The
time for LOCK to assert is predictable
and short, equal to the time to go into
lock, but the time for LOCK to de-assert
must be considered. When the line is
down (i.e. no information received) the
optical receiver circuit may produce ran-
dom noise. It is possible that this random
noise will keep the GD16592 within the
500 ppm (2000 ppm) range of the line
frequency, hence LOCK will remain as-
serted for a non-deterministic time. This
may be prevented by injecting a small
current at the loop filter node, which ac-
tively pulls the PLL out of the lock range
when the output of the phase detector
acts randomly.
The negligible penalty paid is a static
phase error on the sampling time in the
decision gate. However, due to the na-
ture of the phase detector the error will
be small (few degrees), forcing the loop
to be at one edge of the error-function
shaped transfer characteristic of the de-
tector.
DSEL1
DSEL2
SLB
PSEL1
PSEL2
LLB
LLSOP
LLSON
LLCOP
LLCON
Inputs
OD0
DeMUX
OD7
SLSIP
SLSIN
Bang
Bang
Phase
Detector
SIP
SIN
The input amplifier (pin SIP / SIN) is de-
signed as a limiting amplifier with a sen-
sitivity of 10 mV (differential). Standard
LVPECL levels may be applied as well.
The inputs may be either AC or DC cou-
pled. If the inputs are AC coupled the
amplifier features an internal offset can-
celling DC feedback. Notice that the off-
set cancellation will only work when the
input is differential and AC-coupled as
shown in the
Figures 7
and
8
on
page 5.
The serial input SLSIP/SLSIN is selected
when SLB is low.
SELPDH
VCTL
SELTCK
VCO
Clock
Gen.
0
o
/90
o
180
o
/270
o
Phase
Adjust.
CKOUT
LSEL1
LSEL2
LOCK
Divide
by
4
Lock
Detect
VCC
VCCA
CKRF
Divide
by
1/2/4
PFC
GND
GNDA
Outputs
RSEL1
RSEL1
OUCHP
Figure 6.
The GD16592 Multifunction
Receiver.
The CKOUT provides the necessary con-
trol for clocking the received data into the
system ASIC. The phase can be ad-
justed with PSEL1-2 (0°/90°/180°/270°).
Data Sheet Rev. 09
GD16591/GD16592
Page 4 of 16
Practical Considerations
8k
100nF
SIP
SIN
50Ω
100nF
+
LIA
100nF
50Ω
100nF
-
8k
The PCB must be designed with shortest
possible conductors for the signals to the
line interfaces. These connections should
be designed as transmission lines.
De-coupling capacitors should be applied
to each power supply pin. Care should
be taken to reduce ground bounce.
The line loop signal and clock must be
terminated close to the transmitter device
(GD16591).
The system loop signal must be termi-
nated close to the receiver device
(GD16592).
Figure 7.
AC Coupled Input (using internal offset compensation).
8k
SIP
SIN
50Ω
50Ω
+
LIA
-
8k
VTT
Figure 8.
DC Coupled Input (ignoring internal offset compensation). V
TT
depends on
the termination requirements of the previous stage, and the resulting ampli-
tude on the input.
Data Sheet Rev. 09
GD16591/GD16592
Page 5 of 16
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