Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
CLKA
GND
XIN
XOUT
1
8
The FS6182 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6182 is circuitry that implements a
voltage-controlled crystal oscillator when an external
resonator (nominally 13.5MHz) is attached. The VCXO
allows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
A high-resolution phase-locked loop generates three out-
put clocks (CLKA, CLKB, and CLKC) through an array of
post-dividers. All frequencies are ratiometrically derived
from the VCXO frequency. The locking of all the output
frequencies together can eliminate unpredictable artifacts
in video systems.
XTUNE
VDD
CLKC
CLKB
FS6182
2
3
4
7
6
5
Table 1: Crystal / Output Frequencies
DEVICE
FS6182-01
f
XIN
(MHz)
13.500
CLKA
(MHz)
27.000
CLKB
(MHz)
54.000
CLKC
(MHz)
13.500
8-pin (0.150″) SOIC
NOTE: Contact AMI for custom PLL frequencies and 5 volt operation
Figure 2: Block Diagram
XIN
VCXO
XOUT
XTUNE
DIVIDER
ARRAY
PLL
CLKA
CLKB
CLKC
FS6182
This document contains information on a new product. Specifications and information herein are subject to change without notice.
ISO9001
2.27.02
FS6182
VCXO Clock Generator IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
TYPE
DO
P
AI
AO
DO
DO
P
AI
NAME
CLKA
GND
XIN
XOUT
CLKB
CLKC
VDD
XTUNE
Clock Output A
Ground
VCXO Feedback
VCXO Drive
Clock Output B
Clock Output C
Power Supply (+3.3V)
VCXO Tune
DESCRIPTION
3.0
3.1
Functional Block Description
Phase-Locked Loop (PLL)
The on-chip PLLs are a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator to the desired frequency by a ratio of integers.
The frequency multiplication is exact with a zero synthe-
sis error.
the oscillator circuit. The actual amount that changing the
load capacitance alters the oscillator frequency will be
dependent on the characteristics of the crystal as well as
the oscillator circuit itself.
Specifically, the motional capacitance of the crystal (usu-
ally referred to by crystal manufacturers as C
1
), the static
capacitance of the crystal (C
0
), and the load capacitance
(C
L
) of the oscillator determine the warping capability of
the crystal in the oscillator circuit.
A simple formula to obtain the warping capability of a
crystal oscillator is:
6
C
1
×
(
C
L
2
−
C
L
1
)
×
10
∆
f
(
ppm
)
=
2
×
(
C
0
+
C
L
2
)
×
(
C
0
+
C
L
1
)
3.2
Voltage-Controlled Crystal
Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6182 system components.
Loading capacitance for the crystal is internal to the
FS6182. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
total change (from one extreme to the other) in effective
loading capacitance is from 13pF to 35pF.
The oscillator operates the crystal resonator in the paral-
lel-resonant mode. Crystal warping, or the “pulling” of the
crystal oscillation frequency, is accomplished by altering
the effective load capacitance presented to the crystal by
where C
L1
and C
L2
are the two extremes of the applied
load capacitance.
EXAMPLE: A crystal with the following parameters is
used. With C
1
= 0.02pF, C
0
= 5pF, C
L1
= 13pF, and C
L2
=
35pF, the coarse tuning range (peak-to-peak) is:
0
.
02
×
(
35
−
13
)
×
106
∆
f
=
=
305
ppm
.
2
×
(
5
+
35
)
×
(
5
+
13
)
2
ISO9001
2.27.02
FS6182
VCXO Clock Generator IC
4.0
Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage (V
SS
= ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
V
SS
-0.5
-50
-50
-65
-55
MAX.
7
V
DD
+0.5
V
DD
+0.5
50
50
150
125
125
260
2
UNITS
V
V
V
mA
mA
°C
°C
°C
°C
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 4: Operating Conditions
PARAMETER
Supply Voltage
Ambient Operating Temperature Range
SYMBOL
V
DD
T
A
CONDITIONS/DESCRIPTION
3.3V ± 10%
MIN.
3.0
0
TYP.
3.3
MAX.
3.6
70
UNITS
V
°C
3
ISO9001
2.27.02
FS6182
VCXO Clock Generator IC
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
Overall
Supply Current, Dynamic, with Loaded
Outputs
Voltage Controlled Crystal Oscillator
Crystal Resonator Frequency
Crystal Loading Capacitance
Crystal Resonator Motional Capacitance
VCXO Tuning Range
VCXO Tuning Characteristic
Crystal Drive Level
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current *
Low-Level Output Sink Current *
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF
20
mA
f
XTAL
C
L(xtal)
C
1(xtal)
Fundamental Mode
As seen by a crystal connected to XIN and
XOUT (@ V
XTUNE
= mid-range)
f
XTAL
= 13.5MHz; C
L
= 20pF; C
MOT
= 25fF
Note: positive delta F for positive delta V
R
XTAL
=20 ohm; C
L
= 20pF
5
13.5
20
20
300
100
200
18
MHz
pF
fF
ppm
ppm/V
uW
I
OH
I
OL
z
OH
z
OL
I
OSH
I
OSL
V
O
= 2.0V
V
O
= 0.4V
V
O
= 0.1V
DD
; output driving high
V
O
= 0.1V
DD
; output driving low
V
O
= 0V; shorted for 30s, max.
V
O
= 3.3V; shorted for 30s, max.
40
17
25
25
55
55
mA
mA
Ω
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
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