Generates all clocks required for single and two-way
multi-processor (MP) platforms, including:
M
Four differential current-mode Host clock pairs
M
Four 66.67MHz 3.3V CK66 clock outputs
M
Ten 33.3MHz 3.3V PCI clock outputs
M
Two 3.3V Memory Reference clock outputs
M
Two 48MHz 3.3V CK48 clock outputs
M
Two buffered copies of the crystal reference
Control of current-mode Host clocks via IREF current
programming pin and ISEL_0:1 current multiplier pins
Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLLs, and outputs
Spread-spectrum modulation (-0.5% at 31.5kHz) of
SSCG PLL clocks, enabled via SS_EN# input
Supports test mode and tristate output control to fa-
cilitate board testing
Available in a 56-pin SSOP and TSSOP
Crystal
Oscillator
adjust
VDD_R
REF_0:1
VSS_R
VDD_H
HOST_P1:4
HOST_N1:4
VSS_H
VDD_66
•
•
•
CK66_0:3
VSS_66
VDD_P
÷2
PCI_0:9
VSS_P
VDD_M
÷4
MREF_P
MREF_N
VSS_M
VDD_48
•
•
•
PLL
CK48_0:1
VSS_48
FS6232
Figure 2: Pin Configuration
VSS_R 1
56 VDD_M
55 MREF_P
54 MREF_N
53 VSS_M
52 SS_EN#
51 HOST_P1
50 HOST_N1
49 VDD_H
48 HOST_P2
47 HOST_N2
46 VSS_H
45 HOST_P3
44 HOST_N3
43 VDD_H
42 HOST_P4
41 HOST_N4
40 VSS_H
39 IREF
38 VDD
37 VSS
36 VDD_66
35 CK66_0
34 CK66_1
33 VSS_66
32 VSS_66
31 CK66_2
30 CK66_3
29 VDD_66
REF_0 / ISEL_0 2
REF_1 / ISEL_1 3
Table 1: Clock Parameters
CLOCK
GROUP
HOST_P
HOST_N
MREF_P
MREF_N
CK66
PCI
CK48
REF
#
PINS
4
4
1
1
4
10
2
2
3.3V
VDD_H
SUPPLY
VOLTAGE
SUPPLY
GROUP
FREQ.
(MHz)
133.33
100.00
66.67
50.00
66.67
33.33
48.008
14.318
PHASE
0°
180°
0°
180°
0°
0°
0°
0°
SKEW
(MAX)
150ps
Pair to
Pair
-
250ps
300ps
-
-
VDD_R 4
XIN 5
XOUT 6
VSS_P 7
PCI_0 8
PCI_1 9
VDD_P 10
PCI_2 11
PCI_3 12
VSS_P 13
PCI_4 14
PCI_5 15
VDD_P 16
PCI_6 17
PCI_7 18
Pair 1
Pair 2
3.3V
3.3V
3.3V
3.3V
3.3V
VDD_M
VDD_66
VDD_P
VDD_48
VDD_R
Pair 3
FS6232-01
Pair 4
Table 2: Clock Offsets
RELATION
CK66 leads PCI
PHASE
0°
MIN
1.5ns
TYP
MAX
3.5ns
VSS_P 19
PCI_8 20
PCI_9 21
VDD_P 22
SEL133/100# 23
VSS_48 24
CK48_0 / SEL_A 25
CK48_1 / SEL_B 26
VDD_48 27
PWR_DWN# 28
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
9.18.00
IntSKS
FS6232-01
Two-Way MP Motherboard Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
September 2000
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
25
26
35, 34, 31, 30
50, 51
47, 48
44, 45
41, 42
39
54
55
8, 9, 11, 12,
14, 15, 17, 18,
20, 21
28
2
TYPE
DIO
DIO
DO
AO
AO
AO
AO
AI
DO
DO
DO
DI
DIO
NAME
CK48_0
SEL_A
CK48_1
SEL_B
CK66_0:3
HOST_P1
HOST_N1
HOST_P2
HOST_N2
HOST_P3
HOST_N3
HOST_P4
HOST_N4
IREF
MREF_N
MREF_P
PCI_0:9
PWR_DWN#
REF_0
ISEL_0
REF_1
DESCRIPTION
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1
Host clock pair #2; one of six pairs of current-steering differential current-mode outputs
Host clock pair #3; one of six pairs of current-steering differential current-mode outputs
Host clock pair #4; one of six pairs of current-steering differential current-mode outputs
A fixed precision resistor from this pin to ground provides a reference current used for the dif-
ferential current-mode HOST clock outputs
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver
One clock in a pair of outputs provided as a reference clock to a memory clock driver
Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency
Active low spread-spectrum enable turns on spread spectrum modulation
3.3V core power supply
3.3V power supply for CK48 clock outputs
3.3V power supply for CK66 clock outputs
3.3V power supply for the differential HOST clock outputs
3.3V power supply for MREF clock outputs
3.3V power supply for PCI clock outputs
3.3V power supply for the REF clock output and the crystal oscillator
Core ground
Ground for the CK48 clock outputs
Ground for the CK66 clock outputs
Ground for the differential HOST clock outputs
Ground for the MREF clock outputs
Ground for the PCI clock outputs
Ground for the REF clock outputs and the crystal oscillator
14.318MHz crystal oscillator input
14.318MHz crystal oscillator output
SUPPLY
VDD_48
VDD_48
VDD_66
VDD_H
VDD_H
VDD_H
VDD_H
VDD
VDD_M
VDD_M
VDD_P
VDD_48
VDD_R
3
23
52
38
27
29, 36
43, 49
56
10, 16, 22
4
37
24
32, 33
40, 46
53
7, 13, 19
1
5
6
DIO
DI
DI
P
P
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
ISEL_1
SEL133/100#
SS_EN#
VDD
VDD_48
VDD_66
VDD_H
VDD_M
VDD_P
VDD_R
VSS
VSS_48
VSS_66
VSS_H
VSS_M
VSS_P
VSS_R
XIN
XOUT
VDD_R
VDD_48
VDD_M
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD_R
VDD_R
ISO9001
9.18.00
2
FS6232-01
AMERICAN MICROSYSTEMS, INC.
Two-Way MP Motherboard Clock Generator IC
September 2000
2.0
Programming Information
Table 4: Function/Clock Enable Configuration
CONTROL INPUTS
PWR_
DWN#
1
1
1
1
1
1
1
1
0
SEL
133/100#
0
0
0
0
1
1
1
1
X
SEL_A
0
0
1
1
0
0
1
1
X
SEL_B
0
1
0
1
0
1
0
1
X
HOST_P
1:4
100.00
reserved
reserved
tristate
133.33
reserved
reserved
XIN ÷ 2
2
×
IREF
HOST_N
1:4
100.00
reserved
reserved
tristate
133.33
reserved
reserved
XIN ÷ 2
tristate
CLOCK OUTPUTS (MHz)
MREF_P,
MREF_N
50.00
reserved
reserved
tristate
66.67
reserved
reserved
XIN ÷ 4
low
CK66_
0:3
66.67
reserved
reserved
tristate
66.67
reserved
reserved
XIN ÷ 4
low
PCI_
0:9
33.33
reserved
reserved
tristate
33.33
reserved
reserved
XIN ÷ 8
low
CK48_
0:1
48.008
reserved
reserved
tristate
48.008
reserved
reserved
XIN ÷ 2
low
REF
14.318
reserved
reserved
tristate
14.318
reserved
reserved
XIN
low
Table 5: Synthesis Error
CLOCK
HOST_P1:4,
HOST_N1:4
MREF_P,
MREF_N
CK66
PCI
CK48
1.
2.
(1)
3.1
ACTUAL
(MHz)
99.9963
133.3072
49.9982
66.6536
66.6642
33.3321
48.008
DEVIATION
(ppm)
-36.657
-195.924
-36.657
-195.924
-36.657
-36.657
+167
Current Reference
TARGET
(MHz)
100.0000
133.3333
50.0000
66.6667
66.6667
33.3333
48.000
The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is
I
REF
1
×
VDD_I
3
.
=
R
IREF
48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.
Spread spectrum is disabled
3.2
Current Scaling
3.0
HOST Buffer Current Control
The current supplied at the HOST outputs is controlled by
two parameters:
1) the value of the programming resistor from the IREF
pin to ground (VSS), and
2) the multiplier factor determined by the logic setting of
the ISEL_0 and ISEL_1 pins.
The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.
Table 6: Current Multiplier
ISEL_0
0
0
1
1
ISEL_1
0
1
0
1
MULTPLIER
I
O
= 5
×
I
REF
I
O
= 6
×
I
REF
I
O
= 4
×
I
REF
I
O
= 7
×
I
REF
ISO9001
9.18.00
3
FS6232-01
Two-Way MP Motherboard Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
September 2000
Figure 2: Current Reference Circuit
VDD_I (3.3V)
2R
1.1V
Table 8: HOST Buffer Clock Output
Additional
Mirror
Current
Output
Voltage (V)
3.30
3.14
2.97
2.81
HIGH DRIVE CURRENT (mA)
AT PRIMARY SYSTEM CONFIGURATION
MIN.
0.00
-3.03
-5.66
-7.87
-9.67
-11.05
-11.98
-12.52
-12.77
-12.91
-12.99
-13.04
-13.07
-13.08
-13.09
-13.11
-13.12
-13.13
-13.13
-13.14
-13.15
TYP.
0.00
-4.22
-7.68
-10.30
-11.91
-12.56
-12.85
-13.07
-13.26
-13.42
-13.54
-13.64
-13.70
-13.73
-13.75
-13.76
-13.78
-13.79
-13.80
-13.81
-13.82
MAX.
0.00
-5.76
-9.86
-11.85
-12.45
-12.84
-13.16
-13.45
-13.72
-13.96
-14.17
-14.36
-14.52
-14.64
-14.71
-14.74
-14.76
-14.78
-14.80
-14.82
-14.83
R
Mirror
Current
ISEL_0:1
IREF
Reference
Current I
REF
R
IREF
HOST_N
R
S
R
P
HOST_P
R
S
R
P
2.64
2.48
2.31
2.14
1.98
1.81
1.65
Table 7: HOST Current Selection
PROGRAM
RESISTOR
R
IREF
475Ω (1%)
475Ω (1%)
475Ω (1%)
475Ω (1%)
221Ω (1%)
221Ω (1%)
221Ω (1%)
221Ω (1%)
REFERENCE
CURRENT
CURRENT
MULTIPLIER
I
REF
2.32mA
2.32mA
2.32mA
2.32mA
5mA
5mA
5mA
5mA
I
O
= 5
×
I
REF
I
O
= 6
×
I
REF
I
O
= 4
×
I
REF
I
O
= 7
×
I
REF
I
O
= 5
×
I
REF
I
O
= 6
×
I
REF
I
O
= 4
×
I
REF
I
O
= 7
×
I
REF
TRACE
IMPEDANCE
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
30Ω
25Ω
30Ω
25Ω
30Ω
25Ω
30Ω
25Ω
OUTPUT
VOLTAGE
0.71V
0.59V
0.85V
0.71V
0.56V
0.47V
0.99V
0.82V
0.75V
0.62V
0.75V
0.60V
0.50V
1.05V
0.84V
0.90V
1.48
1.32
1.15
0.99
0.82
0.66
0.49
0.33
0.16
0.00
Output Voltage (V)
0
0
-2
1
2
3
Output Current (mA)
-4
-6
-8
-10
-12
-14
-16
-18
-20
NOTE: Shaded row indicates the Primary System Configuration
30Ω
50Ω
90Ω
Max VOH
Data in this table represents nominal characterization data only
ISO9001
9.18.00
4
FS6232-01
AMERICAN MICROSYSTEMS, INC.
Two-Way MP Motherboard Clock Generator IC
September 2000
4.0
Power Management
Table 9: Latency Table
SIGNAL
SIGNAL
STATE
Power
OFF
Power
ON
Output:
Device:
LATENCY
MIN.
2 clocks
2× REF
clocks
3ms
MAX.
3 clocks
3× REF clocks
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.
PWR_
DWN#
0
1
Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.
Figure 3: PWR_DWN# Timing
Any Clock
(internal)
PWR_DWN#
Any Clock
(output)
After REF
output shuts off...
VCO
Crystal
Oscillator
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
3ms until clock is valid
5.0
Dual Function I/O Pins
Figure 4: I/O Pin Programming
Termination
Resistor
Device Solder
Pads
Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10kΩ pull-down resistor to ground is required
for a logic low and a 10kΩ pull-up resistor to the clock
output VDD is required for a logic high. The 10kΩ resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.
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