UTC MJE13005
NPN SILICON POWER
TRANSISTORS
DESCRIPTION
NPN EPITAXIAL SILICON TRANSISTOR
These devices are designed for high-voltage, high-speed
power switching inductive circuits where fall time is critical.
They are particularly suited for 115 and 220 V
SWITCHMODE.
FEATURES
* V
CEO (sus)
400 V
* Reverse Bias SOA with Inductive Loads @ T
C
= 100℃
* Inductive Switching Matrix 2 to 4 Amp, 25 and 100℃
. . . tc @ 3A, 100℃ is 180 ns (Typ)
* 700 V Blocking Capability
* SOA and Switching Applications Information
1
TO-220
APPLICATIONS
* Switching Regulator’s, Inverters
* Motor Controls
* Solenoid/Relay drivers
* Deflection circuits
1: BASE
2: COLLECTOR
3: EMITTER
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Collector-Emitter Voltage
Collector-Emitter Voltage
Emitter Base Voltage
Collector Current- Continuous
- Peak (1)
Base Current- Continuous
- Peak (1)
Emitter Current- Continuous
- Peak (1)
Total Power Dissipation @ T
a
=25℃
Derate above 25℃
Total Power Dissipation @ T
C
=25℃
Derate above 25℃
Operating and Storage Junction Temperature Range
SYMBOL
V
CEO
(sus)
V
CEV
V
EBO
Ic
I
CM
I
B
I
BM
I
E
I
EM
P
D
P
D
T
j
, T
stg
RATINGS
400
700
9
4
8
2
4
6
12
2
16
75
600
-65 ~ +150
UNIT
V
V
V
A
A
A
W
mW/℃
W
mW/℃
℃
THERMAL CHARACTERISTICS
PARAMETER
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Maximum Lead Temperature for Soldering
Purposes: 1/8” from Case for 5 Seconds
(1) Pulse Test : Pulse Width=5ms,Duty Cycle≤10%
SYMBOL
R
θJA
R
θJC
T
L
MAX
62.5
1.67
275
UNIT
℃/W
℃/W
℃
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UNISONIC TECHNOLOGIES CO. LTD
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UTC MJE13005
PARAMETER
*OFF CHARACTERISTICS (1)
Collector-Emitter Sustaining Voltage
Collector Cutoff Current
NPN EPITAXIAL SILICON TRANSISTOR
SYMBOL
V
CEO (SUS)
I
CEV
ELECTRICAL CHARACTERISTICS
(Tc=25℃, unless otherwise noted)
TEST CONDITIONS
Ic=10mA , I
B
=0
V
CEV
=Rated Value, V
BE(off)
=1.5 V
V
CEV
=Rated Value, V
BE(off)
=1.5V,
Tc=100℃
V
EB
=9V, Ic=0
MIN
400
TYP MAX UNIT
V
1
mA
5
1
mA
Emitter Cutoff Current
SECOND BREAKDOWN
Second Breakdown Collector Current
with bass forward biased
Clamped Inductive SOA with Base
Reverse Biased
*ON CHARACTERISTICS (1)
DC Current Gain
Collector-Emitter Saturation Voltage
I
EBO
Is/b
RBSOA
h
FE1
h
FE2
V
CE (sat)
See Figure 11
See Figure 12
Ic=1A, V
CE
=5V
Ic=2A, V
CE
=5V
Ic=1A, I
B
=0.2A
Ic=2A, I
B
=0.5A
Ic=4A, I
B
=1A
Ic=2A, I
B
=0.5A, Ta=100℃
Ic=1A, I
B
=0.2A
Ic=2A, I
B
=0.5A
Ic=2A, I
B
=0.5A, Tc=100℃
Ic=500mA, V
CE
=10V, f=1MHz
V
CB
=10V, I
E
=0, f=0.1MHz
4
65
10
8
60
40
0.5
0.6
1
1
1.2
1.6
1.5
V
Base-Emitter Saturation Voltage
V
BE (sat)
DYNAMIC CHARACTERISTICS
Current-Gain-Bandwidth Product
f
T
Output Capacitance
Cob
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
t
d
Rise Time
t
r
Storage Time
t
s
Fall Time
t
f
* Pulse Test: Pulse Width=300μs, Duty Cycle≤2%
V
MHz
pF
Vcc=125V, Ic=2A, I
B1
=I
B2
=0.4A,
t
P
=25μs, Duty Cycle≤1%
0.025
0.3
1.7
0.4
0.1
0.7
4
0.9
μs
μs
μs
μs
CLASSIFICATION OF HFE2
RANK
RANGE
A
8 ~ 16
B
15 ~ 21
C
20 ~ 26
D
25 ~ 31
E
30 ~ 36
F
35 ~ 40
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UNISONIC TECHNOLOGIES CO. LTD
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UTC MJE13005
NPN EPITAXIAL SILICON TRANSISTOR
RESISTIVE
SWITHCING
TABLE 1.TEST CONDITIONS FOR DYNAMIC PERFORMANCE
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
+5V
1N4933
33
MJE210
L
MR826*
+125V
V
cc
TEST CIRCUITS
0.001μF
5V
P
w
DUTY CYCLE≦10%
t
r
, t
f
≦10ns
68
1k
33 1N4933
2N2222
1k
+5V
1N4933
0.02μF
NOTE
P
W
and V
cc
Adjusted for Desired I
c
R
B
Adjusted for Desired I
B1
270
1k
2N2905
47
1/2W
MJE200
100
-V
BE
(off)
R
B
I
B
T.U.T.
I
c
Vclamp
*SELECTED FOR≧1kV
V
CE
R
B
D1
-4.0V
TUT
R
c
SCOPE
5.1k
51
Coil Data :
FERROXCUBE core #6656
Full Bobbin ( ~ 16 Turns) #16
GAP for 200μH/20 A
Lcoil=200μH
Vcc=20V
V
clamp
=300V
Vcc=125V
Rc=62Ω
D1=1n5820 or
Equiv.
R
B
=22Ω
CIRCUIT
VALUES
OUTPUT WAVEFORMS
TEST WAVEFORMS
t
f
CLAMPED
I
c
I
c(pk)
t
1
V
CE
V
CE
or
V
clamp
TIME
t
2
t
t
f
t
1
=
t
f
UNCLAMPED>t
2
t
t
1
Adjusted to
Obtain Ic
L
coil
(Ic
pk
)
V
cc
L
coil
(Ic
pk
)
V
clamp
Test Equipment
Scope-Tektronics
475 or Equivalent
+10 V
25μS
0
-8V
t
r
, t
f
<10ns
Duty Cycly=1.0%
R
B
and Rc adjusted
for desired I
B
and Ic
t
2
=
RESISTIVE SWITCHING PERFORMANCE
1
0.5
Figure 1. Turn-On Time
10
Figure 2. Turn-Off Time
t
s
V
cc
=125V
I
c
/I
B
=5
T
j
=25℃
TIME, t (µs)
TIME, t (µs)
t
r
0.2
0.1
0.05
V
cc
=125V
I
c
/I
B
=5
T
j
=25℃
5
2
1
0.5
0.3
t
d
@ V
BE(off)
=5V
t
f
0.02
0.010.0
4
0.2
0.10.0
4
0.1
0.2
0.4
1
2
4
0.1
0.2
0.5
1
2
4
COLLECTOR CURRENT, I
C
(AMP)
COLLECTOR CURRENT, I
C
(AMP)
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UNISONIC TECHNOLOGIES CO. LTD
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TRANSIENT THERMAL
RESISTANCE, r(t) (NORMALIZED)
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.01
NPN EPITAXIAL SILICON TRANSISTOR
Figure 3. Typical Thermal Response [Z
θJC
(t)]
D=0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.02
0.05
0.1
0.2
0.5
1
2
Z
θJC(t)
=r(t) R
θJC
R
θJC
=1.67℃/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
j(pk)
-T
C
=P
(pk)
Z
θJC(t)
P
(PK)
t
1
t
2
DUTY CYCLE, D=t
1
/t
2
50
10
0
20
0
50
0
1k
5
10
20
TIME, t (ms)
Figure 4. Forward Bias Safe Operating Area
COLLECTOR CURRENT, I
C
(AMP)
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
5
7
10
20
30
50
Figure 5. Reverse Bias Switching Safe Operating Area
COLLECTOR CURRENT, I
C(pk)
(AMP)
4
5 ms
dc
500μs
V
clamp
Tc≧100℃
I
B1
=2.0A
3
1ms
2
V
BE(off)
=9V
1
UTC MJE13005
0
UTC MJE13005
70 100
200 300
400
500
5V
3V
1.5V
400
500
600
700
800
0
100
200
300
COLLECTOR-EMITTER VOLTAGE, V
CE
(VOLTS)
COLLECTOR-EMITTER CLAMP VOLTAGE,
V
CE
(VOLTS)
1
Figure 6. Forward Bias Power Derating
SECOND BREAKDOWN
DERATING
POWER DERATING FACTOR
0.8
0.6
0.4
THERMAL
DERATING
0.2
0
20
40
60
80
100
120
140
160
CASE TEMPERATURE, T
C
(℃)
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
-V
CE
limits of the transistor that must be observed for reliable
operation; e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 4 is based on T
C
= 25℃; T
j(pk)
is variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated when T
C
≥25℃.
Second breakdown limitations do not
derate the same as thermal limitations. Allowable current at the voltages shown on Figure 4 may be found at any
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UNISONIC TECHNOLOGIES CO. LTD
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QW-R203-018,C
UTC MJE13005
NPN EPITAXIAL SILICON TRANSISTOR
case temperature by using the appropriate curve on Figure 6.
T
j(pk)
may be calculated from the data in Figure 10. At high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be sustained simultaneously during turn-off, in most cases,
with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe
level at or below a specific value of collector current. This can be accomplished by several means such as active
clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias Safe
Operating Area and represents the voltage-current conditions during reverse biased turn-off. This rating is verified
under clamped conditions so that the device is never subjected to an avalanche mode. Figure 5 gives the complete
RBSOA characteristics.
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. DC Current Gain
COLLECTOR-EMITTER VOLTAGE,
V
CE
(VOLTS)
100
70
2
Figure 8. Collector Saturation Region
T
j
=25℃
1.6
DC CURRENTGAIN, hFE
T
j
=150℃
25℃
50
30
20
Ic=1A
1.2
2A
3A
4A
-55℃
V
CE
=2V
- - - - - -V
CE
=5V
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
0.8
10
7
5
0.4
0
0.03
0.05
0.1
0.2 0.3
0.5 0.7
1
2
3
COLLECTOR CURRENT, I
C
(AMP)
BASE CURRENT, I
B
(AMP)
BASE-EMITTER VOLTAGE, V
BE
(VOLTS)
Figure 9. Base-Emitter Voltage
1.3
Figure 10. Collector-Emitter Saturation Voltage
COLLECTOR-EMITTER SATURATION
VOLTAGE, VCE(sat) (VOLTS)
0.55
1.1
V
BE(sat)
@ I
C
/I
B
=4
- - - - - -V
BE(on)
@ V
CE
=2V
T
j
=-55℃
25℃
Ic/I
B
=4
0.45
0.9
0.35
T
j
=-55℃
25℃
0.7
0.25
25℃
0.5
0.15
150℃
0.3
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
150℃
0.05
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
COLLECTOR CURRENT, I
C
(AMP)
COLLECTOR CURRENT, I
C
(AMP)
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QW-R203-018,C