Preliminary Data Sheet PD60185-C
IR1176
SYNCHRONOUS RECTIFIER DRIVER
Features
•
Provides constant and proper gate drive to power
Product Summary
V
dd
I
O+/- (peak)
F
max
Max lead time
5Vdc
4A/4A
2MHz
500nsec
•
•
•
•
•
•
MOSFETs regardless of transformer output
Minimizes loss due to power MOSFET body
drain diode conduction
Stand alone operation - no ties to primary side
Schmitt trigger input with double pulse suppress-
ion allows operation in noisy environments
High peak current drive capability - 4A
High speed operation - 2MHz
Adaptable to multiple topologies
Description
The IR1176 is a high speed CMOS controller designed
to drive N-channel power MOSFETs used as synchro-
nous rectifiers in high current, high frequency forward
converters with output voltages equal or below 5V
DC
.
Schmitt trigger inputs with double pulse suppression
allow the controller to operate in noisy environments.
The circuit does not require any ties to the primary
side and derives its operating power directly from
the secondary. The circuit functions by anticipating
transformer output transitions, then turns the power
MOSFETs on or off before the transitions of the trans-
former to minimize body drain diode conduction and
reduce associated losses. Turn on/off lead time can
be adjusted to accommodate a variety of power
MOSFET sizes and circuit conditions. The IR1176 also
provides gate drive overlap/dead-time control via
external components to further minimize diode con-
duction by nulling effects of secondary loop and de-
vice package inductance.
Packages
IR1176S
20 Lead Surface Mount
(SSOP-20)
IR1176SS
20 Lead SOIC (MS-013AC)
IR1176
20 Lead PDIP
(MS-001AD)
IR1176
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
Symbol
V
dd
I
in
P
D
Definition
Supply voltage
Input clamp current
Power dissipation
(SSOP-20)
(SOIC)
(PDIP)
Min.
—
—
—
—
—
—
—
—
—
—
—
—
-55
—
Max.
7
+/- 10
400
—
—
28.5
20
28.1
90.5
45
62.4
150
150
300
Units
V
DC
mA
DC
mW
—
—
Rth
JC
Thermal resistance
(SSOP-20) junction-to-case
(SOIC) junction-to-case
(PDIP) junction-to-case
°C/W
Rth
JA
Thermal resistance
(SSOP-20) junction-to-ambient
(SOIC) junction-to-ambient
(PDIP) junction-to-ambient
T
J
T
S
T
L
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
°C
Recommended Operating Conditions
Symbol
Vdd
T
A
Freq
Rbias
UV
Xin
Cd1/Cd2
Definition
Supply voltage operating range
Ambient temperature
Operating frequency
Required bias resistor (+/- 1%)
Voltage at UVSET pin
Maximum voltage at X1 and X2 inputs
Capacitance at pins DTIN1 and DTIN2
Min.
—
-40
Typ.
5
—
—
34.0
—
—
—
Max.
—
85
500
—
2.25
5.6
100
Units
V
DC
°C
KHz
K
Ω
V
DC
V
DC
pF
250
—
1.75
—
—
2
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IR1176
Dynamic Electrical Characteristics
Vdd=5V, T
A
= 25
o
C, Rbias = 34.0K unless otherwise specified.
Symbol
Vdd
Iqdd
Freq
UVSET+
UVSET-
Vxth+
Vxth-
Tadv
Td
Isink
(peak)
Isource
(peak)
VOH
VOL
tio
Definition
Supply voltage operating range
Vdd quiescent current (x1 = x2 = 0V or 5V, Iout = 0)
Operating frequency
UVSET positive going threshold
UVSET negative going threshold
X1/X2 Input positive going threshold
X1/X2 Input negative going threshold
Externally adjustable lead time (advance)
Externally adjustable dead-time for Q1 and Q2
Q1,Q2 output sink current (Vdd=5.0V,
pulsed, 10 usec)
Q1,Q2 output source current (Vdd=5.0V,
pulsed, 10 usec)
Q1, Q2 High level voltage (Iout = 20mA)
Q1, Q2 Low level voltage (Iout = 20mA)
Input to output delay (PLL bypassed, cross coupled
mode)
Min.
4.0
—
100
1.10
0.8
—
—
—
20
—
Typ.
—
4
—
—
—
1.4
1.0
—
—
4
Max.
5.25
5
2000
1.4
1.1
—
—
500
—
—
Units
V
DC
A
KHz
V
V
V
DC
V
DC
nsec
nsec
—
4
—
A
—
—
—
Vdd- 0.20
0.10
20
—
—
—
V
nsec
tr
tf
Vtr
Gate turn-on rise time (C1=1000pf, Vdd=5V)
Gate turn-off fall time (C1=1000pf, Vdd=5V)
Cross-over voltage (Vdd=5Vdc, DTIN shorted to
DTOUT, C1=1000pf) Fig. 3
—
—
—
20
20
2.5
—
—
—
nsec
nsec
V
DC
K
Ω
V
DC
nsec
µA
DC
V
DC
KHz/
Volt
Rbias
Vbias
Tjitter
Ichgpump
Vchgpump
Kvco_dc
Required bias resistor (1%)
Voltage at Rbias pin
Phase-lock loop output jitter
Charge pump output current (at VFLTR pin)
Charge pump output voltage (at VFLTR pin)
PLL Vco DC gain (per design)
—
—
-20
—
1.3
—
34.0
1.25
—
50
1.5
62
—
—
20
—
1.7
—
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3
IR1176
Lead Definitions and Assignments
Symbol Description
AVDD
Q1
DTIN1
RADV1
VFLTR1
RVCO1
X1
VDD
UVSET
RBIAS
AVSS
X2
RVCO2
VFLTR2
RADV2
DTIN2
VSS
Q2
Power - + 5 V
DC
to MOSFET drivers
Output - gate drive for Q1 power MOSFET
Input - sets dead time for Q1 - used with DTOUT1
Output - sets lead time (advance) for Q1
Output - PLL loop filter for Q1 output
Output - sets PLL center frequency for Q1 output
Input - transformer input for Q1
Power - +5 Vdc for internal logic
Input - sets UVLO+
If this pin is pulled below 1.25VDC externally, then both Q1 and Q2
outputs will be at Vss (disabled)
Output - connected to 34.0K +/- 1% resistor - sets operating current
Ground for MOSFET driver supply (VDD)
Input - transformer input for Q2
Output - sets PLL center frequency for Q2 output
Output - PLL loop filter for Q2
Output - sets lead time (advance) for Q2
Input - sets dead time for Q2 - used with DTOUT2
Ground for logic supply (AVDD)
Output - gate drive for Q2 power MOSFET
DTOUT1 Output - sets dead time for Q1 output - used with DTIN1
DTOUT2 Output - sets dead time for Q2 - used with DTIN2
1
*VDD
2
Q1
3
DTOUT2
4
DTIN2
5
RADV1
6
VFLTRI
7
RVCO1
8
X1
9
AVDD
10
UVSET
Q2
VSS
DTOUT1
DTIN1
RADV2
VFLTR2
RVCO2
X2
AVSS
RBIAS
20
19
18
17
16
15
14
13
12
11
1
*VDD
2
Q1
3
DTOUT2
4
DTIN2
5
RADV1
6
VFLTRI
7
RVCO1
8
X1
9
AVDD
10
UVSET
Q2
VSS
DTOUT1
DTIN1
RADV2
VFLTR2
RVCO2
X2
AVSS
RBIAS
20
19
18
17
16
15
14
13
12
11
1
*VDD
2
Q1
3
DTOUT2
4
DTIN2
5
RADV1
6
VFLTRI
7
RVCO1
8
X1
9
AVDD
10
UVSET
20
VSS
19
DTOUT1
18
DTIN1
17
RADV2
16
VFLTR2
15
RVCO2
14
X2
13
AVSS
12
RBIAS
11
Q2
IR1176S
(SSOP-20)
4
IR1176SS
SOIC (wide body)
IR1176
PDIP
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IR1176
Fig. 1 Typical application circuit when supply Vout < 5.0 V
DC
Fig. 2 Typical application circuit when supply Vout = 5.0 V
DC
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