Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
F
EATURES
•
Two LVCMOS / LVTTL outputs
•
Differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Maximum output frequency: 350MHz
•
Output skew: 15ps (maximum)
•
Part-to-part skew: 600ps (maximum)
•
Additive phase jitter, RMS: 0.03ps (typical)
•
Small 8 lead SOIC package saves board space
•
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS83026I-01 is a low skew, 1-to-2 Dif-
ferential-to-LVCMOS/LVTTL Fanout Buffer and
HiPerClockS™
a member of the HiPerClockS ™ family of
High Perfor mance Clock Solutions from
ICS. The differential input can accept most dif-
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts. The small 8-lead SOIC footprint makes this device ideal
for use in applications with limited board space.
IC
S
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DD
CLK
nCLK
OE
1
2
3
4
8
7
6
5
V
DDO
Q0
Q1
GND
Q0
CLK
nCLK
Q1
OE
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
V
DD
CLK
nCLK
OE
1
2
3
4
8
7
6
5
V
DDO
Q0
Q1
GND
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
83026BMI-01
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Type
Description
Positive supply pin.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Output enable. When HIGH, outputs are enabled. When LOW, outputs are in
Pullup
High Impedance State. LVCMOS / LVTTL interface levels.
Power supply ground.
Clock output. LVCMOS / LVTTL interface levels.
Clock output. LVCMOS / LVTTL interface levels.
Output supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
Name
V
DD
CLK
nCLK
OE
GND
Q1
Q0
V
DDO
Power
Input
Input
Input
Power
Output
Output
Power
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
V
DD
, V
DDO
= 3.3V
Output Impedance
V
DD
= 3.3V, V
DDO
= 2.5V
V
DD
= 3.3V, V
DDO
= 1.8V
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
V
DD
= 3.465V, V
DDO
= 1.95V
51
51
7
8
10
Test Conditions
Minimum
Typical
4
17
16
15
Maximum
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
Ω
Ω
T
ABLE
3. C
ONTROL
F
UNCTION
T
ABLE
Input
OE
0
1
Outputs
Q0, Q1
HiZ
Active
83026BMI-01
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
101.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
8 Lead SOIC
8 Lead TSSOP
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.71V
TO
3.465V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
1.71
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.89
10
3
Units
V
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.375V
TO
3.465V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
OE
OE
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.135V
V
DDO
= 2.375V
-150
2.6
1.8
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
V
V
V
Output High Voltage; NOTE 1
V
OL
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information section,
"Output Load Test Circuit" diagrams.
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
83026BMI-01
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
OE
OE
OE
OE
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
V
V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
I
OH
= -100µA
I
OH
= -2mA
I
OL
= 100µA
I
OL
= 2mA
www.icst.com/products/hiperclocks.html
3
-150
V
DDO
- 0.2
V
DDO
- 0.45
0. 2
0.45
V
V
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
nCLK
CLK
nCLK
CLK
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
0.15
1. 3
V
DD
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
T
ABLE
3D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.71V
TO
3.465V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
Peak-to-Peak Input Voltage; NOTE 1
V
CMR
Common Mode Input Voltage; NOTE 2, 3
GND + 0.5
NOTE 1: V
PP
can exceed 1.3V provided that there is sufficient offset level to keep V
IL
> 0V.
NOTE 2: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS, refer to
Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
IJ 350MHz
1.3
1.9
Test Conditions
Minimum
Typical
Maximum
350
2.5
15
900
0.03
20% to 80%
IJ 66MHz
67MHz
≤
IJ 166MHz
15 0
48
45
800
52
55
Units
MHz
ns
ps
ps
ps
ps
%
%
%
167MHz
≤
IJ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 6.
83026BMI-01
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
IJ 350MHz
Minimum
1.5
Typical
2.0
Maximum
350
2.6
15
750
0.03
20% to 80%
IJ 66MHz
67MHz
≤
IJ 166MHz
150
48
46
800
52
54
Units
MHz
ns
ps
ps
ps
ps
%
%
%
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Duty Cycle
167MHz
≤
IJ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Duty Cycle
IJ 350MHz
1.9
2.5
Test Conditions
Minimum
Typical
Maximum
350
3.1
15
600
0.03
20% to 80%
IJ 66MHz
67MHz
≤
IJ 166MHz
200
48
43
900
52
57
Units
MHz
ns
ps
ps
ps
ps
%
%
%
167MHz
≤
IJ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83026BMI-01
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 16, 2006
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