CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Operating Specifications
Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are @ T
A
= +25°C and
V
DD
= 3.3V.
CONDITIONS
MIN
(Note 12)
2.7
1.8
TYP
MAX
(Note 12)
5.5
5.5
UNIT
V
V
SYMBOL
V
DD
V
BAT
PARAMETER
Main Power Supply
Backup Power Supply
Electrical Specifications
SYMBOL
I
DD1
PARAMETER
Supply Current with I
2
C Active
CONDITIONS
V
DD
= 2.7V
V
DD
= 5.5V
I
DD2
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
V
DD
= 2.7V
V
DD
= 5.5V
V
DD
= V
SDA
= V
SCL
= 2.7V
V
DD
= V
SDA
= V
SCL
= 5.5V
V
BAT
= 1.8V, V
DD
= V
SDA
= V
SCL
=
0V
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= 0V
I
BATLKG
V
TRIP
Battery Input Leakage
V
BAT
Mode Threshold
V
DD
= 5.5V, V
BAT
= 1.8V
1.8
2.2
30
50
10
800
850
MIN
(Note 12)
TYP
MAX
(Note 12)
500
800
2.5
3.5
10
20
1000
1200
UNIT
µA
µA
mA
mA
µA
µA
nA
nA
5
5
3, 6, 7
3, 6, 7
3, 4, 5
NOTES
3, 4, 5
I
DD3
I
BAT
100
2.6
nA
V
mV
mV
V/ms
7
7,10
7,10
8
V
TRIPHYS
V
TRIP
Hysteresis
V
BATHYS
V
DD SR-
IRQ/F
OUT
V
OL
Output Low Voltage
V
DD
= 5V
I
OL
= 3mA
V
DD
= 1.8V
I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
V
BAT
Hysteresis
V
DD
Negative Slew Rate
0.4
0.4
100
400
V
V
nA
FN6370 Rev 3.00
August 18, 2008
Page 3 of 25
ISL12024
EEPROM Specifications
PARAMETER
EEPROM Endurance
EEPROM Retention
Temperature
75°C
TEST CONDITIONS
MIN
(Note 12)
2,000,000
50
TYP
MAX
UNITS
Cycles
Years
Serial Interface (I
2
C) Specifications
DC Electrical Specifications
SYMBOL
V
IL
V
IH
Hysteresis
V
OL
I
LI
I
LO
PARAMETER
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
I
OL
= 4mA
V
IN
= 5.5V
V
IN
= 5.5V
TEST CONDITIONS
MIN
(Note 12)
-0.3
0.7 x V
DD
0.05 x V
DD
0
100
100
0.4
TYP
MAX
(Note 12)
0.3 x V
DD
V
DD
+ 0.3
UNITS
V
V
V
V
nA
nA
AC Electrical Specifications
SYMBOL
f
SCL
t
IN
t
AA
t
BUF
PARAMETER
SCL Frequency
Pulse width Suppression Time at Any pulse narrower than the max spec is
SDA and SCL Inputs
suppressed.
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of V
DD
, until SDA
Data Valid
exits the 30% to 70% of V
DD
window.
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
SDA crossing 70% of V
DD
during a STOP
condition, to SDA crossing 70% of V
DD
during
the following START condition.
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
DD
.
From SDA falling edge crossing 30% of V
DD
to
SCL falling edge crossing 70% of V
DD
.
From SDA exiting the 30% to 70% of V
DD
window, to SCL rising edge crossing 30% of
V
DD
.
From SCL rising edge crossing 70% of V
DD
to
SDA entering the 30% to 70% of V
DD
window.
From SCL rising edge crossing 70% of V
DD
, to
SDA rising edge crossing 30% of V
DD
.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
DD
.
From SCL falling edge crossing 30% of V
DD
,
until SDA enters the 30% to 70% of V
DD
window.
1300
TEST CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12)
400
50
900
UNITS NOTES
kHz
ns
ns
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
1300
600
600
600
100
ns
ns
ns
ns
ns
t
HD:DAT
t
SU:STO
t
HD:STO
t
DH
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
0
600
600
0
ns
ns
ns
ns
FN6370 Rev 3.00
August 18, 2008
Page 4 of 25
ISL12024
AC Electrical Specifications
SYMBOL
Cpin
t
WC
t
R
t
F
Cb
R
PU
PARAMETER
SDA and SCL Pin Capacitance
Non-Volatile Write Cycle Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or
SCL
SDA and SCL Bus Pull-up
Resistor Off-chip
From 30% to 70% of V
DD
(Note 11)
From 70% to 30% of V
DD
(Note 11)
Total on-chip and off-chip. (Note 11)
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2k~2.5k.
For Cb = 40pF, max is about 15k~20k
20 +
0.1 x Cb
20 +
0.1 x Cb
10
1
12
(Continued)
TEST CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12)
10
20
300
300
400
UNITS NOTES
pF
ms
ns
ns
pF
k
11
11
11
11
NOTES:
3. IRQ/F
OUT
Inactive.
4. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz
5. V
DD
> V
BAT
+V
BATHYS
6. Bit BSW = 0 (Standard Mode), ATR = 00h, V
BAT
1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
9. Parameter is not 100% tested.
10. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end
of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device
specification.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
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