SRAM
MT5C1008
128K x 8 SRAM
WITH DUAL CHIP ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin CSOJ (SOJ)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
FEATURES
• High Speed: 12, 15, 20, 25, 35, 45, 55, 70, 85,
100 and 120 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\, CE2, and OE\
options.
• All inputs and outputs are TTL compatible
• Micross Components uses die type Cy7C109B from
Cypress -6-T SRAM cell design
32-Pin LCC (ECA)
4 3 2 1 32 31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
85ns access
100ns access
120ns access
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
• 2V data retention/low power
MARKING
-12 (contact factory)
-15
-20
-25
-35
-45
-55*
-70*
-85*
-100*
-120*
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
A12
A14
A10
6
NC
V
CC
A15
CE2
32-Pin Flat Pack (F)
29
28
27
26
25
24
23
22
21
WE
\
A13
A8
A9
A11
OE
\
A10
CE1
\
DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1008 SRAM employs high-speed, low
power CMOS designs using a four-transistor memory cell, and
are fabricated using double-layer metal, double-layer polysili-
con technology.
For design flexibility in high-speed memory appli-
cations, this device offers dual chip enables (CE1\, CE2) and
output enable (OE\). These control pins can place the outputs
in High-Z for additional flexibility in system design. All de-
vices operate from a single +5V power supply and all inputs
and outputs are fully TTL compatible.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH
and CE1\ and OE\ go LOW. The devices offer a reduced
power standby mode when disabled, allowing system designs
to achieve low standby power requirements.
The “L” version offers a 2V data retention mode,
reducing current consumption to 1mA maximum.
C
CW
EC
ECA
F
DCJ
SOJ
L
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
For more products and information
please visit our web site at
www.micross.com
MT5C1008
Rev. 6.9 06/11
Micross Components reserves the right to change products or specifications without notice.
1
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
SRAM
MT5C1008
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
A
A
A
A
A
A
A
A
A
ROW DECODER
DQ8
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
DQ1
(LSB)
CE1\
CE2
COLUMN DECODER
(LSB)
OE\
WE\
POWER
DOWN
A A A A A A A A
NOTE:
The two least significant row address bits (A8 and A6) are encoded using gray code.
TRUTH TABLE
MODE
STANDBY
STANDBY
READ
READ
WRITE
OE\
X
X
L
H
X
CE1\
H
X
L
L
L
CE2
X
L
H
H
H
WE\
X
X
H
H
L
DQ
HIGH-Z
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
MT5C1008
Rev. 6.9 06/11
Micross Components reserves the right to change products or specifications without notice.
2
SRAM
MT5C1008
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range (Vcc)...............................-.5V to +6.0V
Storage Temperature ....................................-65C to +150C
Short Circuit Output Current (per I/O)….......................20mA
Voltage on any Pin Relative to Vss................-.5V to Vcc+1 V
Max Junction Temperature**.......................................+150C
Power Dissipation .............................................................1 W
*Stresses at or greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
will affect reliability. Refer to page 17 of this datasheet for a
technical note on this subject.
** Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C & -45
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V<V
IN
<V
CC
Output(s) disabled
0V<V
OUT
<V
CC
I
OH
=-4.0mA
I
OL
=8.0mA
CONDITIONS
SYM
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MAX
-20
-25
150
140
MIN
2.2
-0.5
-10
-10
2.4
MAX
V
CC
+0.5
0.8
10
10
UNITS
V
V
μA
μA
V
NOTES
1
1, 2
1
1
0.4
V
PARAMETER
CONDITIONS
SYM
-12
250
-15
180
-35
135
-45
125
UNITS NOTES
mA
3
Power Supply
Current: Operating
CE\ < V
IL
; OE\, WE\, and CE2>V
IH
I
CCSP
V
CC
= MAX, f = MAX = 1/t
RC
(MIN)
Output Open
*L version only
I
CCLP *
CE\=V
IH,
CE2=V
IL
; Other Inputs at
<V
IL
, >V
IH
, V
CC
= MAX
f = 0 Hz
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
-0.2V
V
IH
> V
CC
-0.2V; F = 0 Hz
I
SBT
250
180
140
130
125
115
mA
Power Supply
Current: Standby
25
25
25
25
25
25
mA
I
SBC
10
10
10
10
10
10
mA
CAPACITANCE
DESCRIPTION
Input Capacitance (A0-A16)
Output Capacitance
Input Capacitance (CE\, WE\, OE\)
MT5C1008
Rev. 6.9 06/11
CONDITIONS
T
A
= 25 C, f = 1MHz
V
CC
= 5V
o
SYM
C
I
C
O
C
I
MAX
12
14
20
UNITS
pF
pF
pF
NOTES
4
4
4
Micross Components reserves the right to change products or specifications without notice.
3
SRAM
MT5C1008
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C & -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-12
-15
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
12
12
3
3
7
7
0
7
12
11
11
0
0
11
8
0
5
7
15
12
12
0
0
12
8
0
5
7
0
7
20
15
15
0
0
15
10
0
5
9
3
3
7
7
0
8
25
20
20
0
0
20
15
0
5
10
15
15
15
3
3
8
7
0
10
35
25
25
0
0
25
20
0
5
15
20
20
20
3
3
10
10
0
15
45
35
35
0
5
35
20
0
5
20
25
25
25
3
3
15
15
0
20
35
35
35
3
3
20
20
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
MT5C1008
Rev. 6.9 06/11
Micross Components reserves the right to change products or specifications without notice.
4
SRAM
MT5C1008
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
480
Q
30
Q
255
5 pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-2V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
8.
9.
10.
11.
12.
13.
4.
5.
6.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
CE2 timing is the same as CE1\ timing. The
waveform is inverted.
Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V, f=0
V
CC
= 2V
I
CCDR
1.0
mA
CONDITIONS
SYMBOL
V
DR
MIN
2
MAX
---
UNITS NOTES
V
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
4.5V
V > 2V
DR
CDR
V
DR
t
R
CE1\
CE2
MT5C1008
Rev. 6.9 06/11
V
IH
V
IL
V
IH
V
IL
DON’T CARE
<V
SS
+ 0.2V
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
5
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