Features
•
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz (ATmega165PA/645P)
– Up to 20 MIPS Throughput at 20 MHz
(ATmega165A/325A/325PA/645A/3250A/3250PA/6450A/6450P)
– On-Chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– In-System Self-programmable Flash Program Memory
• 16K Bytes (ATmega165A/ATmega165PA)
• 32K Bytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 64K Bytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– EEPROM
• 512 Bytes (ATmega165A/ATmega165PA)
• 1K bytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 2K bytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Internal SRAM
• 1K Bytes (ATmega165A/ATmega165PA)
• 2K Bytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 4K Bytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
QTouch
®
library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
I/O and Packages
– 54/69 Programmable I/O Lines
– 64/100-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
Speed Grade:
– ATmega 165A/165PA/645A/645P: 0 - 16 MHz @ 1.8 - 5.5V
– ATmega325A/325PA/3250A/3250PA/6450A/6450P: 0 - 20MHz @ 1.8 - 5.5V
Temperature range:
– -40°C to 85°C Industrial
Ultra-Low Power Consumption (picoPower devices)
– Active Mode:
• 1 MHz, 1.8V: 215 µA
• 32 kHz, 1.8V: 8 µA (including Oscillator)
– Power-down Mode: 0.1 µA at 1.8V
– Power-save Mode: 0.6 µA at 1.8V (Including 32 kHz RTC
•
8-bit
Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash
ATmega165A
ATmega165PA
ATmega325A
ATmega325PA
ATmega3250A
ATmega3250PA
ATmega645A
ATmega645P
ATmega6450A
ATmega6450P
Preliminary
Summary
•
•
•
•
•
•
•
•
Note:
1.
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
Rev 8285AS–AVR–10/10
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P
1. Pin Configurations
1.1
Pinout - TQFP and QFN/MLF
64A (TQFP)and 64M1 (QFN/MLF) Pinout
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P
56
PF5 (ADC5/TMS)
55
PF6 (ADC6/TDO)
57
PF4 (ADC4/TCK)
54
PF7 (ADC7/TDI)
Figure 1-1.
61
PF0 (ADC0)
60
PF1 (ADC1)
59
PF2 (ADC2)
58
PF3 (ADC3)
AVCC
AREF
53 GND
GND
52 VCC
51 PA0
50 PA1
64
63
62
49 PA2
48 PA3
47 PA4
46 PA5
45 PA6
44 PA7
43 PG2
42 PC7
41 PC6
40 PC5
39 PC4
38 PC3
37 PC2
36 PC1
35 PC0
34
33
PG1
PG0
DNC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
INDEX CORNER
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND 22
(TOSC2) XTAL2 23
(TOSC1) XTAL1 24
(ICP1) PD0 25
(INT0) PD1 26
PD2 27
PD3 28
(OC2A/PCINT15) PB7 17
(T1) PG3 18
(T0) PG4 19
RESET/PG5 20
VCC 21
PD4 29
PD5 30
PD6 31
Note:
The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol-
dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen
from the board.
PD7 32
2
8285AS–AVR–10/10
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P
1.2
Pinout - 100A (TQFP)
Pinout ATmega3250A/ATmega3250PA/ATmega6450A/ATmega6450P
Figure 1-2.
TQFP
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF4 (ADC4/TCK)
PF7 (ADC7/TDI)
PH7 (PCINT23)
PH6 (PCINT22)
PH5 (PCINT21)
PH4 (PCINT20)
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
AGND
AVCC
AREF
GND
DNC
DNC
DNC
DNC
DNC
VCC
PA0
PA1
77
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
DNC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
VCC
GND
DNC
(PCINT24) PJ0
(PCINT25) PJ1
DNC
DNC
DNC
DNC
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
INDEX CORNER
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA2
PA3
PA4
PA5
PA6
PA7
PG2
PC7
PC6
DNC
PH3 (PCINT19)
PH2 (PCINT18)
PH1 (PCINT17)
PH0 (PCINT16)
DNC
DNC
DNC
DNC
PC5
PC4
PC3
PC2
PC1
PC0
PG1
PG0
RESET/PG5
(TOSC2) XTAL2
(TOSC1) XTAL1
(INT0) PD1
GND
(OC2A/PCINT15) PB7
(ICP1) PD0
(T1) PG3
(T0) PG4
VCC
DNC
DNC
DNC
PD2
PD3
PD4
PD5
PD6
(PCINT26) PJ2
(PCINT27) PJ3
(PCINT28) PJ4
(PCINT29) PJ5
(PCINT30) PJ6
DNC
PD7
3
8285AS–AVR–10/10
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P
2. Overview
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit microcon-
troller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, this
microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
2.1
Block Diagram
Block Diagram
Figure 2-1.
GND
VCC
PF0 - PF7
PA0 - PA7
PC0 - PC7
PORTF DRIVERS
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT
DATA BUS
AVCC
AGND
AREF
ADC
CALIB. OSC
INTERNAL
OSCILLATOR
OSCILLATOR
JTAG TAP
DATA DIR.
REG. PORTH
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
PORTH DRIVERS
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
PH0 - PH7
DATA REGISTER
PORTH
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
RESET
DATA DIR.
REG. PORTD
DATA REG.
PORTG
DATA DIR.
REG. PORTG
PORTD DRIVERS
PORTG DRIVERS
PD0 - PD7
PG0 - PG4
DATA DIR.
REG. PORTJ
CONTROL
LINES
ALU
EEPROM
PORTJ DRIVERS
AVR CPU
STATUS
REGISTER
PJ0 - PJ6
DATA REGISTER
PORTJ
USART
UNIVERSAL
SERIAL INTERFACE
SPI
ANALOG
COMPARATOR
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
+
-
PORTE DRIVERS
PORTB DRIVERS
PE0 - PE7
PB0 - PB7
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
4
8285AS–AVR–10/10
XTAL1
XTAL2
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P provides the
following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write
capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines,
32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging
support and programming, three flexible Timer/Counters with compare modes, internal and
external interrupts, a serial programmable USART, Universal Serial Interface with Start Condi-
tion Detector, an 8-channel, 10-bit ADC, a programmable
Watchdog
Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to con-
tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O mod-
ules except asynchronous timer and ADC, to minimize switching noise during ADC conversions.
In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleep-
ing. This allows very fast start-up combined with low-power consumption.
Atmel offers the QTouch
®
library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression
®
(AKSTM
™
) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel devise is a powerful microcontroller that provides a highly flexible and
cost effective solution to many embedded control applications.
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P AVR is sup-
ported with a full suite of program and system development tools including: C Compilers, Macro
Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
5
8285AS–AVR–10/10
stm32/stm8
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