Datasheet> 器件分类 > 存储> 存储> IS61LF12836-8.5BI

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IS61LF12836-8.5BI: 产品描述Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA119, PLASTIC, BGA-119; 产品类别存储存储; 文件大小110KB，共15页; 制造商Integrated Silicon Solution ( ISSI )

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IS61LF12836-8.5BI概述

Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA119, PLASTIC, BGA-119

IS61LF12836-8.5BI规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
零件包装代码	BGA
包装说明	PLASTIC, BGA-119
针数	119
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
Is Samacsys	N
最长访问时间	8.5 ns
最大时钟频率 (fCLK)	100 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B119
JESD-609代码	e0
长度	22 mm
内存密度	4718592 bit
内存集成电路类型	CACHE SRAM
内存宽度	36
功能数量	1
端子数量	119
字数	131072 words
字数代码	128000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	128KX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA119,7X17,50
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	240
电源	2.5,3.3 V
认证状态	Not Qualified
座面最大高度	2.41 mm
最大待机电流	0.02 A
最小待机电流	3.14 V
最大压摆率	0.3 mA
最大供电电压 (Vsup)	3.63 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	14 mm
Base Number Matches	1

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IS61LF12832

IS61LF12836

128K x 32, 128K x 36 SYNCHRONOUS

FLOW-THROUGH STATIC RAM

FEATURES

•

Fast access times: 7.5 ns and 8.5 ns

Internal self-timed write cycle

Individual Byte Write Control and Global Write

Clock controlled, registered address, data inputs

and control signals

Interleaved or linear burst sequence control

using MODE input

Three chip enables for simple depth expansion

and address pipelining

Common data inputs and data outputs

JEDEC 100-Pin TQFP and

119-pin PBGA package

Single +3.3V +10%, –5% power supply

Power-down snooze mode

2.5V I/O voltage

Industrial temperature available

ISSI

PRELIMINARY INFORMATION

MAY 2001

DESCRIPTION

The

ISSI

IS61LF12832 and IS61LF12836 are high-speed

synchronous static RAM designed to provide a burstable,

high-performance memory for high speed networking and

communication applications. It is organized as 131,072

words by 32 bits or 36 bits, fabricated with

ISSI

's advanced

CMOS technology. The device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs into

a single monolithic circuit. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1

controls DQa,

BW2

controls DQb,

BW3

controls DQc,

BW4

controls DQd, conditioned by

BWE

being LOW. A LOW

input would cause all bytes to be written.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally

and controlled by the

ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

7.5

8.8

113

8.5

100

Units

MHz

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION

05/28/00

Rev. 00A

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