3.0 kV RMS/3.75 kV RMS
Quad Digital Isolators
Data Sheet
FEATURES
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals
(pending)
UL recognition
3000 V rms/3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM
= 849 V peak
CQC certification per GB4943.1-2011
Backward compatibility
ADuM140E1/ADuM141E1/ADuM142E1
pin-compatible
with
ADuM1400/ADuM1401/ADuM1402
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, SOIC package
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
FUNCTIONAL BLOCK DIAGRAMS
V
DD1 1
GND
1 2
V
IA
3
ADuM140D/ADuM140E
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
16
15
14
13
12
11
10
9
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
NIC/V
E2
GND
2
13119-101
13119-103
13119-102
V
IB 4
V
IC 5
V
ID 6
DISABLE
1
/NIC
7
GND
1 8
NOTES
1. NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
2. PIN 7 IS DISABLE
1
AND PIN 10 IS NIC FOR THE ADuM140D, AND
PIN 7 IS NIC AND PIN 10 IS V
E2
FOR THE ADuM140E.
Figure 1.
ADuM140D/ADuM140E
Functional Block Diagram
V
DD1 1
GND
1 2
V
IA 3
V
IB 4
V
IC 5
V
OD 6
DISABLE
1
/V
E1 7
GND
1 8
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ADuM141D/ADuM141E
16
15
14
13
12
11
10
9
V
DD2
GND
2
V
OA
V
OB
V
OC
V
ID
DISABLE
2
/V
E2
GND
2
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
NOTES
1. PIN 7 IS DISABLE
1
AND PIN 10 IS DISABLE
2
FOR THE ADuM141D,
AND PIN 7 IS V
E1
AND PIN 10 IS V
E2
FOR THE ADuM141E.
Figure 2.
ADuM141D/ADuM141E
Functional Block Diagram
V
DD1 1
GND
1 2
V
IA 3
V
IB 4
V
OC 5
V
OD 6
DISABLE
1
/V
E1 7
GND
1 8
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
ADuM142D/ADuM142E
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
IC
11
V
ID
10
DISABLE
2
/V
E2
9
GND
2
GENERAL DESCRIPTION
The
ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E
1
are quad-channel digital isolators
based on Analog Devices, Inc.,
iCoupler®
technology. Combining
high speed, complementary metal-oxide semiconductor (CMOS)
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices and other
integrated couplers. The maximum propagation delay is 13 ns
with a pulse width distortion of less than 3 ns at 5 V operation.
Channel matching is tight at 3.0 ns maximum.
The
ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E
data channels are independent and
are available in a variety of configurations with a withstand
voltage rating of 3.0 kV rms or 3.75 kV rms (see the Ordering
Guide). The devices operate with the supply voltage on either side
ranging from 1.8 V to 5 V, providing compatibility with lower
voltage systems as well as enabling voltage translation functionality
across the isolation barrier.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
NOTES
1. PIN 7 IS DISABLE
1
AND PIN 10 IS DISABLE
2
FOR THE ADuM142D,
AND PIN 7 IS V
E1
AND PIN 10 IS V
E2
FOR THE ADuM142E.
Figure 3.
ADuM142D/ADuM142E
Functional Block Diagram
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available, by which the outputs transition to a pre-
determined state when the input power supply is not applied or the
inputs are disabled. The
ADuM140E1/ADuM141E1/ADuM142E1
are pin-compatible with the
ADuM1400/ADuM1401/ADuM1402.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Other patents are pending.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation ............................... 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—2.5 V Operation ............................ 7
Electrical Characteristics—1.8 V Operation ............................ 9
Insulation and Safety Related Specifications .......................... 11
Package Characteristics ............................................................. 11
Regulatory Information ............................................................. 12
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 13
Data Sheet
Recommended Operating Conditions .................................... 14
Absolute Maximum Ratings ......................................................... 15
ESD Caution................................................................................ 15
Truth Tables ................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
Typical Performance Characteristics ........................................... 20
Applications Information .............................................................. 22
Overview ..................................................................................... 22
Printed Circuit Board (PCB) Layout ....................................... 22
Propagation Delay Related Parameters ................................... 23
Jitter Measurement ..................................................................... 23
Insulation Lifetime ..................................................................... 23
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
11/15—Rev. A to Rev. B
Added 16-Lead, Narrow Body SOIC Package ................ Universal
Changes to Title, Features Section, and General Description
Section ................................................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Table 5 ............................................................................ 7
Changes to Table 7 ............................................................................ 9
Added Table 9; Renumbered Sequentially .................................. 11
Changes to Table 10 and Table 11 ................................................ 11
Changes to Regulator Information Section................................. 12
Changes to Table 12........................................................................ 12
Added Table 13 ............................................................................... 12
Changes to Table 14........................................................................ 13
Added Table 15 and Figure 4; Renumbered Sequentially ......... 14
Changes to Figure 5 Caption ......................................................... 14
Changes to Endnote 3, Table 17, and Table 19 Title .................. 15
Added Table 18 ............................................................................... 15
Changes to Surface Tracking Section........................................... 23
Changes to Calculation and Use of Parameters Example
Section .............................................................................................. 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
9/15—Rev. 0 to Rev. A
Added ADuM141D/ADuM141E ..................................... Universal
Added ADuM142D/ADuM142E ..................................... Universal
Changes to Features and Figure 1 ...................................................1
Delete Figure 2; Renumbered Sequentially ....................................1
Added Figure 2 and Figure 3; Renumbered Sequentially ............1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................5
Changes to Table 4.............................................................................6
Changes to Table 5.............................................................................7
Change to Table 6 ..............................................................................8
Changes to Table 7.............................................................................9
Changes to Table 8.......................................................................... 10
Changes to Table 11 ....................................................................... 11
Changes to Table 12 ....................................................................... 12
Changes Table 15 ............................................................................ 13
Changes to Table 17 ....................................................................... 14
Added Figure 7, Figure 8, and Table 19; Renumbered
Sequentially ..................................................................................... 16
Added Figure 9, Figure 10, and Table 20 ..................................... 16
Added Figure 13 and Figure 16 .................................................... 18
Changes to Figure 17 and Figure 18 ............................................ 19
Changes to Overview Section and Figure 19 .............................. 20
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
4/15—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
SPECIFICATIONS
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
Min
6.6
150
4.8
Typ
Max
Unit
ns
Mbps
ns
ns
ps/°C
ns
Test Conditions/Comments
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|t
PLH
− t
PHL
|
Between any two units at the
same temperature, voltage, and load
7.2
0.5
1.5
13
3
6.1
t
PSKCD
t
PSKOD
0.5
0.5
490
70
3.0
3.0
ns
ns
ps p-p
ps rms
See the Jitter Measurement section
See the Jitter Measurement section
V
IH
V
IL
V
OH
0.7 × V
DDx
0.3 × V
DDx
V
DDx
− 0.1
V
DDx
− 0.4
V
DDx
V
DDx
−
0.2
0.0
0.2
+0.01
−3
9
+0.01
V
V
V
V
I
Ox2
= −20 μA, V
Ix
= V
IxH3
I
Ox2
= −4 mA, V
Ix
= V
IxH3
I
Ox2
= 20 μA, V
Ix
= V
IxL4
I
Ox2
= 4 mA, V
Ix
= V
IxL4
0 V ≤ V
Ix
≤ V
DDx
V
E2
= 0 V
DISABLE
1
= V
DDx
0 V ≤ V
Ox
≤ V
DDx
Logic Low
Input Current per Channel
V
E2
Enable Input Pull-Up Current
DISABLE
1
Input Pull-Down Current
Tristate Output Current per Channel
Quiescent Supply Current
ADuM140D/ADuM140E
V
OL
I
I
I
PU
I
PD
I
OZ
−10
−10
−10
0.1
0.4
+10
15
+10
V
V
μA
μA
μA
μA
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (Q)
I
DD2 (Q)
ADuM141D/ADuM141E
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (Q)
I
DD2 (Q)
ADuM142D/ADuM142E
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (Q)
I
DD2 (Q)
Dynamic Supply Current
Dynamic Input
Dynamic Output
I
DDI (D)
I
DDO (D)
1.2
2.0
12.0
2.0
1.6
1.9
10.0
6.0
1.6
1.6
7.2
8.4
0.01
0.02
2.2
2.72
20.0
2.92
2.46
2.62
17.0
10.0
2.46
2.46
11.5
11.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA/Mbps
mA/Mbps
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
Rev. B | Page 3 of 27
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Parameter
Undervoltage Lockout
Positive V
DDx
Threshold
Negative V
DDx
Threshold
V
DDx
Hysteresis
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity
7
Symbol
UVLO
V
DDxUV+
V
DDxUV−
V
DDxUVH
t
R
/t
F
|CM
H
|
|CM
L
|
1
2
Data Sheet
Min
Typ
1.6
1.5
0.1
2.5
100
100
Max
Unit
V
V
V
ns
kV/µs
kV/µs
Test Conditions/Comments
75
75
10% to 90%
V
Ix
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
I
Ox
is the Channel x output current, where x = A, B, C, or D.
3
V
IxH
is the input side logic high.
4
V
IxL
is the input side logic low.
5
V
I
is the voltage input.
6
E0 is the
ADuM140E0/ADuM141E0/ADuM142E0
models, D0 is the
ADuM140D0/ADuM141D0/ADuM142D0
models, E1 is the
ADuM140E1/ADuM141E1/ADuM142E1
models, and D1 is the
ADuM140D1/ADuM141D1/ADuM142D1
models. See the Ordering Guide section.
7
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V
O
) > 0.8 V
DDx
. |CM
L
| is the maximum common-
mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 2. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM140D/ADuM140E
Supply Current Side 1
Supply Current Side 2
ADuM141D/ADuM141E
Supply Current Side 1
Supply Current Side 2
ADuM142D/ADuM142E
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
I
DD1
I
DD2
I
DD1
I
DD2
I
DD1
I
DD2
6.8
2.1
5.8
4.0
4.3
5.3
10
3.7
10.3
6.85
7.7
8.7
7.8
3.9
7.0
5.5
6.0
6.7
12
5.7
10.9
8.5
9.3
10.1
11.8
9.2
11.4
10.3
10.3
11.0
17.4
13
15.9
14.0
14.2
14.9
mA
mA
mA
mA
mA
mA
Rev. B | Page 4 of 27
Data Sheet
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ V
DD1
≤ 3.6 V, 3.0 V ≤ V
DD2
≤ 3.6 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
V
E2
Enable Input Pull-Up Current
DISABLE
1
Input Pull-Down Current
Tristate Output Current per Channel
Quiescent Supply Current
ADuM140D/ADuM140E
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
Min
6.6
150
4.8
Typ
Max
Unit
ns
Mbps
ns
ns
ps/°C
ns
Test Conditions/Comments
Within PWD limit
Within PWD limit
50% input to 50% output
|t
PLH
− t
PHL
|
Between any two units at the same
temperature, voltage, and load
6.8
0.7
1.5
14
3
7.5
t
PSKCD
t
PSKOD
0.7
0.7
580
120
3.0
3.0
ns
ns
ps p-p
ps rms
See the Jitter Measurement section
See the Jitter Measurement section
V
IH
V
IL
V
OH
V
OL
I
I
I
PU
I
PD
I
OZ
0.7 × V
DDx
0.3 × V
DDx
V
DDx
− 0.1
V
DDx
− 0.4
V
DDx
V
DDx
− 0.2
0.0
0.2
+0.01
−3
9
+0.01
V
V
V
V
V
V
μA
μA
μA
μA
I
Ox2
= −20 μA, V
Ix
= V
IxH3
I
Ox2
= −2 mA, V
Ix
= V
IxH3
I
Ox2
= 20 μA, V
Ix
= V
IxL4
I
Ox2
= 2 mA, V
Ix
= V
IxL4
0 V ≤ V
Ix
≤ V
DDx
V
E2
= 0 V
DISABLE
1
= V
DDx
0 V ≤ V
Ox
≤ V
DDx
−10
−10
−10
0.1
0.4
+10
15
+10
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (Q)
I
DD2 (Q)
ADuM141D/ADuM141E
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (Q)
I
DD2 (Q)
ADuM142D/ADuM142E
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (Q)
I
DD2 (Q)
1.2
2.0
12.0
2.0
1.5
1.8
9.8
5.7
1.6
1.6
7.2
8.4
2.12
2.68
19.6
2.8
2.36
2.52
16.7
9.7
2.4
2.4
11.2
11.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
Rev. B | Page 5 of 27
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