RMKHT (CNHT)
www.vishay.com
Vishay Sfernice
High Temperature (230 °C) Wirebondable Thin Film Chip Resistors
and Resistor Networks
FEATURES
• Operating temperature range: - 55 °C; + 215 °C
• Storage temperature: - 55 °C; + 230 °C
• Wirebondable (aluminum pads)
• Aluminum or gold pads
• Large selection of sizes available
• Custom networks available on request (CNHT)
• Temperature coefficient down to 15 ppm/°C
(- 55 °C; + 215 °C)
• Tolerance down to 0.05 %
• Temperature coefficient remains at 15 ppm/°C after long
term storage at 230 °C
• Material categorization: For definitions of compliance
please see
www.vishay.com/doc?99912
INTRODUCTION
For applications such as down hole applications, the need
for parts able to withstand very severe conditions
(temperature as high as 215 °C powered or up to 230 °C
un-powered) has leaded Vishay Sfernice to push out the
limit of the thin film technology.
Designers might read the application note “Power
Dissipation Considerations in High Precision Vishay
Sfernice Thin Film Chip Resistors and Arrays
(P, PRA, etc…) (High Temperature Application)
www.vishay.com/doc?53047
in conjunction with this
datasheet to help them to properly design their PCBs and
get the best performances of the RMKHT.
Vishay Sfernice research and development engineers will
be willing to support any customer design considerations.
TYPICAL PERFORMANCE
ABS
TCR
TOL.
25 ppm/°C
ABS
0.05 %
Note
(1)
When applicable (networks only)
TRACKING
(1)
2 ppm/°C
RATIO
(1)
0.02 %
MECHANICAL SPECIFICATIONS
Resistive element
Substrate material
Bonding pads
Passivation
Back metallization
(2)
(2)
Nichrome (NiCr)
Silicon (size 22, 33, 55, 515) - alumina (other sizes)
Aluminum (Al) or gold (Au)
Silicon nitride (Si3N4)
Gold on nickel barrier
Note
When applicable (only on alumina substrate)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2000
Drift (%)
With Pd (T
j
= 230 °C)
T = 185 °C
T = 200 °C
T = 215 °C
T = 230 °C
4000
6000
8000
t (h)
10 000
12 000
14 000
Note
• TCR (- 55 °C; + 215 °C) remains unchanged after 15 000 h storage
Revision: 26-Mar-13
Document Number: 60075
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
RMKHT (CNHT)
www.vishay.com
SCHEMATIC
WIREBONDABLE CHIP RESISTORS
RMKHT22
R
R
RMKHT33
R2 R1
1
R1
RMKHT515
R
R1 = R2 = R
2
3
R1 = R2 = R3 = R4 = R
R2
4
RMKHT55
RMKHT48
7
6
R4
8
Vishay Sfernice
WIREBONDABLE RESISTORS NETWORKS
R3
5
8
RMKHT408
7
6
5
15
14
RMKHT816
13 12
11
10
R8
16
RMKHT0603
R
RMKHT0805
R
1
2
3
4
R1 = R2 = R4 = R4 = R
R1
R2
R3
R4
1
R1 R2 R3 R4 R5 R6 R7
9
8
2
3
4 5
6
7
R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8 = R
RMKHT2010
8
RMKHT1206
RMKHT508
7
6
5
13
12
RMKHT914
11 10
9
8
R9
R2
R
R
R1
R4
R5
R3
14
NC
R2
R4
R3
R6
R5
R8
NC
7
R1
R7
1
2
3
4
R1 = R2 = R4 = R4 = R5 = R
1
2
3 4
5
6
R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8 = R9 = R
POWER DERATING CURVE
Rated Power (%)
350
300
250
200
150
100
50
0
0
50
100
150
200
250
Ambient Temperature in °C
Revision: 26-Mar-13
Document Number: 60075
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
RMKHT (CNHT)
www.vishay.com
PATTERN
WIREBONDABLE CHIP RESISTORS
RMKHT22
B
C
E
A
G
F
D
F
RMKHT515
B
E
C
G
F
D
RMKHT55
B
E
Vishay Sfernice
WIREBONDABLE RESISTORS NETWORKS
RMKHT33
C
F
G
B
C
G
A H
D
E
A
E
D
H
B
C
RMKHT48
A
G
A
F
D
RMKHT408
RMKHT508
B
F
C
RMKHT0603
B
E
A
F
D
A
C
RMKHT0805
B
E
C
A
G
D
E
D
F
RMKHT1206
B
E
C
F
G
RMKHT816
RMKHT914
B
C
A
D
A
F
RMKHT2010
B
E
C
I
J
H
D
E
DIMENSIONS
in millimeters
A
D
SERIES
RMKHT33
RMKHT48
A
B
C
D
± 0.05 ± 0.05 max.
0.83
2
1.6
1.7
0.83
2
2.6
3.4
0.4
E
F
G
H
I
J
0.4 0.08 0.16 0.3 0.22 0.6
0.1 0.39 0.57 0.12 0.69
F
RMKHT408
RMKHT508
RMKHT816
D
0.08
0.11
0.96
E
F
G
RMKHT914
0.4 0.11 0.36 0.65 1.25
0.4. 0.13 0.25 0.62 0.69 0.35 0.47 0.225
DIMENSIONS
in millimeters
SERIES
RMKHT22
RMKHT55
RMKHT515
RMKHT0603
RMKHT0805
RMKHT2010
A
B
C
± 0.05 ± 0.05 max.
0.58
1.32
1.32
0.9
1.25
2.64
0.58
1.32
3.75
1.8
2.05
3.2
5.23
0.4
0.4
0.4
0.45
0.45
0.45
0.45
0.08 0.354 0.354
0.26
0.16
0.87
3.3
1.02
0.68 0.265 1.365
1.03 0.265 1.615
1.505 0.29
2.74
2.42 0.518 4.54
RMKHT1206
1.725
Revision: 26-Mar-13
Document Number: 60075
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
RMKHT (CNHT)
www.vishay.com
Vishay Sfernice
TCR
(1)
- 55 °C; + 215 °C
± ppm/°C
15, 30
15, 30
15, 30
15, 30
15, 30
15, 30
15, 30
POWER RATING
(2)
P
70 °C
W
0.05
0.25
0.5
0.125
0.2
0.33
1
POWER RATING
(2)
P
215 °C
W
0.005
0.025
0.05
0.0375
0.06
0.1
0.2
STANDARD ELECTRICAL SPECIFICATIONS
- Bare Resistors Chips
MODEL
RMKHT22
RMKHT55
RMKHT515
RMKHT0603
RMKHT0805
RMKHT1206
RMKHT2010
SIZE
0202
0505
0515
0603
0805
1206
2010
RESISTANCE
RANGE
10 to 500K
10 to 2M
20 to 5M
10 to 320K
10 to 725K
10 to 2.7M
10 to 6M
TOLERANCE
±%
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
PERFORMANCES
- Bare Resistors Chips
TEST
Limiting voltage
Operating temperature range
Max. temperature resistive element
Max. substrate temperature
Load life stability
Storage temperature range
Shelf life stability
SPECIFICATIONS
From 75 V to 300 V (depending on size)
(3)
- 55 °C; + 215 °C
220 °C
230 °C
0.35 %
- 55 °C; + 230 °C
0.6 % typ. (0.8 % max.)
CONDITIONS
2000 h/220 °C (ambient) at Pn
15 000 h/230 °C
STANDARD ELECTRICAL SPECIFICATIONS
- Bare Resistors Networks
RESISTANCE ABSOLUTE
RANGE
(1)
TOLERANCE
±%
100 to 1M
100 to 800K
100 to 400K
500 to 400K
100 to 400K
100 to 200K
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
RATIO
TOLERANCE
±%
0.02, 0.05, 0.2, 0.1
0.02, 0.05, 0.2, 0.1
0.02, 0.05, 0.2, 0.1
0.02, 0.05, 0.2, 0.1
0.02, 0.05, 0.2, 0.1
0.02, 0.05, 0.2, 0.1
ABSOLUTE
RATIO
TCR
(2)
TCR
- 55 °C; + 215 °C - 55 °C; + 215 °C
± ppm/°C
± ppm/°C
15, 30
15, 30
15, 30
15, 30
15, 30
15, 30
2, 5
2, 5
2, 5
2, 5
2, 5
2, 5
POWER
RATING
(2)
P
70 °C
W
PER
RESISTOR
0.10
0.10
0.10
0.10
0.10
0.10
POWER
RATING
(2)
P
215 °C
W
PER
RESISTOR
0.010
0.010
0.010
0.010
0.010
0.010
MODEL
SIZE
RMKHT33
RMKHT48
RMKHT408
RMKHT508
RMKHT816
RMKHT914
0303
0808
0610
0610
0714
0714
PERFORMANCES
- Bare Resistors Networks
TEST
Limiting voltage
Operating temperature range
Max. temperature resistive element
Max. substrate temperature
Load life stability
Load life stability on ratio
Storage temperature range
Shelf life stability
Notes
(1)
Temperature Coefficient
Bare Resistors Chips
Y
E
Bare Resistors Networks
10 ppm/°C abs.
1 ppm/°C tracking
- 55 °C; + 155 °C
15 ppm/°C abs.
2 ppm/°C tracking
- 55 °C; + 215 °C
25 ppm/°C abs.
2 ppm/°C tracking
- 55 °C; + 155 °C
E
30 ppm/°C abs.
5 ppm/°C tracking
- 55 °C; + 215 °C
Pn is intended with no back side metallized. For power handling improvement, please refer to application note 53047: Power Dissipation
Cosiderations in High Precision Vishay Sfernice Thin Film Chip Resistors and Arrays (High Temperature Applications)
www.vishay.com/doc?53047
and consult Vishay Sfernice
See table next page
It is possible to dissipate up to 0.3 W, but there will be an additional drift of 0.1 % after load life
Y
Document Number: 60075
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
10 ppm/°C
15 ppm/°C
25 ppm/°C
30 ppm/°C
SPECIFICATIONS
100 V
- 55 °C; + 215 °C
220 °C
230 °C
0.35 %
0.35 %
- 55 °C; + 230 °C
0.6 % typ. (0.8 % max.)
CONDITIONS
2000 h/220 °C (ambient) at Pn
2000 h/220 °C (ambient) at Pn
15 000 h/230 °C
- 55 °C; + 155 °C
- 55 °C; + 215 °C
- 55 °C; + 155 °C
- 55 °C; + 215 °C
(2)
(3)
(4)
Revision: 26-Mar-13
RMKHT (CNHT)
www.vishay.com
OHMIC RANGE
(1)
CT: Y
CT: E
MIN.
MAX.
MIN.
MAX.
50
300 k
10
500 k
1 k
750 k
10
2 M
1 k
2 M
20
5 M
39
320 k
10
320 k
39
511 k
10
725 k
39
1.8 M
10
2.7 M
39
3 M
10
6 M
Vishay Sfernice
OHMIC RANGE
SERIES
33
48
408
508
816
914
MIN.
1 k
1 k
1 k
1 k
1 k
1 k
CT: Y
MAX.
250 k
200 k
200 k
200 k
200 k
200 k
MIN.
100
100
100
500
100
100
CT: E
MAX.
1 M
800 k
400 k
400 k
400 k
200 k
SERIES
22
55
515
0603
0805
1206
2010
Note
(1)
Best possible tolerance:
0.5 %: 10
to < 20
0.1 %: 20
to < 39
0.05 %: 39
to max. ohmic value
SIZE
22
55
515
0603
0805
1206
2010
LIMITING VOLTAGE
in V
100 V
100 V
100 V
75 V
150 V
200 V
300 V
POPULAR OPTION
Back side metalized
Option to order: 06 (not available for sizes 22, 33, 55, 515)
Please refer to Application Note 53047 “Power
Considerations in High Precision Vishay Sfernice Thin Film
Chip Resistors and Arrays (High Temperature Applications)
www.vishay.com/doc?53047
to evaluate performances
improvement depending on process (brazing or gluing).
Choice of PCB will be determinant.
GLOBAL PART NUMBERING INFORMATION
- Bare Resistors Chips
Bare Chip Resistors
R
M
K
H
SIZE
22
55
515
0603
0805
1206
2010
T
0
6
TCR
Y
E
0
3
Y
VALUE
1
0
0
1
B
A
PADS
0
6
OPTION
Blank
=
No option
06
=
Back side
metallized
GLOBAL MODEL
RMKHT
TOLERANCE
W
= 0.05 %
B
= 0.1 %
D
= 0.5 %
F
=1%
The first 3 digits are
significant figures and the
last digit specifies the
number of zeros to follow.
R designates decimal point
10R0
= 10
3901
= 3900
1004
= 1 M
AA
(1)
A:
Aluminum
G:
Gold
GLOBAL PART NUMBERING INFORMATION
- Bare Resistors Networks
Bare Resistors Networks
R
M
K
H
T
8
1
6
E
1
0
0
1
B
W
A
0
6
GLOBAL
MODEL
RMKHT
SIZE
33
48
408
508
816
914
TCR
Y
E
VALUE
The first 3 digits are
significant figures and
the last digit specifies
the number of zeros to
follow. R designates
decimal point
10R0
= 10
3901
= 3900
1004
= 1 M
AA
(1)
ABS.
TOLERANCE
W
= 0.05 %
B
= 0.1 %
D
= 0.5 %
F
=1%
TOLERANCE
RATIO
P
= 0.02 %
W
= 0.05 %
D
= 0.5 %
B
= 0.1 %
PADS
A:
Aluminum
G:
Gold
OPTION
Blank
=
No option
06
=
Back side
metallized
Note
(1)
For more than three significant digits an alphabetical code will be used (AA to ZZ) and a cross table will be provided
Revision: 26-Mar-13
Document Number: 60075
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
