PF1510
Power management integrated circuit (PMIC) for low power
application processors
Rev. 1.0 — 23 May 2018
Data sheet: advance information
1
General description
The PF1510 is a power management integrated circuit (PMIC) designed specifically for
use with i.MX processors on low-power portable, smart wearable and Internet-of-Things
(IoT) applications. It is also capable of providing full power solution to i.MX 7ULP, i.MX
6SL, 6UL, 6ULL and 6SX processors.
With three high efficiency buck converters, three linear regulators, DDR reference and
RTC supply, the PF1510 can provide power for a complete system, including application
processors, memory, and system peripherals.
1.1 Features and benefits
This section summarizes the PF1510 features:
•
Input voltage VIN from 5V bus, USB, or AC adapter (4.1 V to 6.0 V)
–
Linear front-end input LDO (1500 mA input limit)
–
Up to 6.5 V input operating range
–
VIN can withstand transient and DC inputs from 0 V up to +22 V
•
Buck converters:
–
SW1, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps
–
SW2, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps
–
SW3, 1.0 A; 1.8 V to 3.3 V in 100 mV steps
–
Internal digital soft start
–
Quiescent current 1.0 μA in ULP mode with light load
–
Peak efficiency > 90 %
–
Dynamic voltage scaling on SW1 and SW2
–
Modes: forced PWM quasi-fixed frequency mode, adaptive variable-frequency mode
–
Programmable output voltage, current limit and soft start
•
LDO regulators
–
LDO1, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode
–
LDO2, 1.8 to 3.3 V, 400 mA
–
LDO3, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode
–
Quiescent current < 1.5 μA in Low-power mode
–
Programmable output voltage
–
Soft start and ramp
–
Current limit protection
–
USB_PHY low dropout linear regulator
–
LDO2P7 always on regulator output
•
LDO/switch supply
–
RTC supply VSNVS 3.0 V, 2.0 mA
–
Coin cell charger
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
•
DDR memory reference voltage, VREFDDR, 0.5 to 0.9 V, 10 mA
•
OTP (One time programmable) memory for device configuration
–
User programmable start-up sequence, timing, soft-start and power-down sequence
–
Programmable regulator output voltages
2
•
I C interface
•
User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes
•
Ambient temperature range −40 °C to 105 °C
PF1510
1.2 Applications
•
•
•
•
•
•
•
Low-power IoT applications
Wireless game controllers
Embedded monitoring systems
Home automation
POS
E-Reader
Smart mobile/wearable devices
PF1510
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: advance information
Rev. 1.0 — 23 May 2018
2 / 100
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
PF1510
2
Application diagram
PF1510
VREFDDR
DDR MEMORY
SW2
DDR MEMORY INTERFACE
Low-power application
processor
SW1
GPS
MIPI
PROCESSOR ARM CORE
PROCESSOR REAL-TIME
SOC/GPU
FLASH
NAND - NOR
INTERFACES
SD/MMC/
NAND MEMORY
WIFI
EXTERNAL AMP
MICROPHONES
SPEAKERS
LDO1
SW3
LDO2
LDO3
BLUETOOTH
VSNVS
SNVS_IN
AUDIO
CODEC
CONTROL SIGNALS
I
2
C COMMUNICATION
LI-CELL
CHARGER
USB_PHY
PARALLEL CONTROL
/ GPIO
I2C COMMUNICATION
SENSORS
COIN CELL
FRONT-END
LDO
5.0 V FROM ADAPTER OR USB
aaa-028828
Figure 1. Application diagram
PF1510
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: advance information
Rev. 1.0 — 23 May 2018
3 / 100
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
PF1510
2.1 Functional block diagram
PF1510 FUNCTIONAL BLOCK DIAGRAM
FRONT-END LDO
(Up to 6.5 V input, 1500 mA,
22 V surge)
BUCK1
(0.6 V to 1.3875 V, 1.0 A, DVS;
1.1 V to 3.3 V, 1.0 A, no DVS)
BUCK2
(0.6 V to 1.3875 V, 1.0 A, DVS;
1.1 V to 3.3 V, 1.0 A, no DVS)
LOGIC AND CONTROL
I
2
C/processor interface/
regulator control/
OTP
(flexible configuration)
LDO1
(0.75 V to 3.3 V, 300 mA)
LDO2
(1.8 V to 3.3 V, 400 mA)
LDO3
(0.75 V to 3.3 V, 300 mA)
USBPHY
(4.9 V or 3.3 V, 60 mA)
LDO2P7
(2.7 V, 5.0 mA)
BUCK3
(1.8 V to 3.3 V, no DVS)
VSNVS (RTC SUPPLY)
(3.0 V, 2.0 mA)
DDR VOLTAGE REFERENCE
(V
INREFDDR
/2, 10 mA)
aaa-028829
Figure 2. Functional block diagram
PF1510
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: advance information
Rev. 1.0 — 23 May 2018
4 / 100
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
PF1510
2.2 Internal block diagram
RESETBMCU
VDDOTP
PWRON
ONKEY
VDDIO
INTB
SDA
SCL
WDI
SW1FB
SW1IN
SW1LX
EPAD
EA AND
DRIVER
SW1 DVS
AND MISC
REFERENCE
PF1510
ANALOG CORE
(REFERENCE
AND BIAS CURRENT)
VCORE
LDO
VCORE
PF1510
DIGITAL CORE
AND STATE MACHINE
VDIG
LDO
VDIG
SW2FB
SW2IN
SW2LX
EPAD
EA AND
DRIVER
SW2 DVS
AND MISC
REFERENCE
WATCHDOG
TIMER
OTP MEMORY
COIN CELL
CHARGER
LICELL
VSNVS
VSNVS
VSYS
32 kHz CLOCK
SW3FB
SW3IN
SW3LX
EPAD
VREFDDR
DIVIDE INPUT
BY 2
LDO1
EA AND
DRIVER
SW3
AND MISC
REFERENCE
16 kHz CLOCK
LDO2P7
LDO
USBPHY
LDO
VIN
USBPHY
LDO2P7
LDO3
LDO3
INTERNAL
LOGIC
ICTEST
LDO1OUT
LDO1OUT
LDO2OUT
digital signal(s)
analog reference(s)
16 kHz clock / derivative
32 kHz clock / derivative
LDO3OUT
LDO1IN
LDO1IN
LDO2IN
LDO3IN
aaa-028830
Figure 3. Internal block diagram
3
Orderable parts
The PF1510 is available only with preprogrammed configurations. These preprogrammed
devices are identified using the program codes from
Table 1,
which also list the
associated NXP reference designs where applicable. Details of the OTP programming for
each device can be found in
Table 51.
PF1510
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: advance information
Rev. 1.0 — 23 May 2018
5 / 100
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