®
RT8179B
Dual-Output PWM Controller with 2 Integrated Drivers for
AMD SVI2 Mobile CPU Power Supply
General Description
The RT8179B is a dual-output PWM controller, and is
compliant with AMD SVI2 Voltage Regulator Specification
to support both CPU core (VDD) and Northbridge portion
of the CPU (VDDNB). The RT8179B features CCRCOT
(Constant Current Ripple Constant On-Time) with G-NAVP
(Green-Native AVP), which is Richtek's proprietary
topology. G-NAVP makes it an easy setting controller to
meet all AMD AVP (Adaptive Voltage Positioning) VDD/
VDDNB requirements. The droop is easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses the
interface to issue VOTF Complete and to send digitally
encoded voltage and current values for the VDD and
VDDNB domains. It can operate in diode emulation mode
and reach up to 90% efficiency in different modes according
to different loading conditions. The RT8179B provides
special purpose offset capabilities by pin setting. The
RT8179B also provides power good indication, over
current indication (OCP_L) and dual OCP mechanism for
AMD SVI2 CPU core and NB. It also features complete
fault protection functions including over voltage, under
voltage and negative voltage.
Features
1-Phase (VDD) + 1-Phase (VDDNB) PWM Controller
2 Embedded MOSFET Drivers
G-NAVP
TM
Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Build-in ADC for V
OUT
and I
OUT
Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanisms
DVID Turbo Boost Compensation
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over Current Indicator
40-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
AMD SVI2 Mobile CPU
Laptop Computer
Simplified Application Circuit
RT8179B
OCP_L
PHASE
SVC
To CPU
SVD
SVT
PHASEA
MOSFET
V
VDDNB
MOSFET
V
VDD
Copyright
©
2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8179B-05 August 2016
www.richtek.com
1
RT8179B
Ordering Information
RT8179B
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
½
Pin Configuration
(TOP VIEW)
UGATE
PHASE
LGATE
PVCC
LGATEA
PHASEA
UGATEA
BOOTA
TONSETA
PGOOD
40 39 38 37 36 35 34 33 32 31
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
½
BOOT
TONSET
ISEN1N
ISEN1P
VSEN
FB
COMP
RGND
IMON
V064
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
41
30
29
28
27
26
25
24
23
22
21
GND
PGOODA
EN
ISENA1P
ISENA1N
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
RT8179BGQW : Product Number
RT8179B
GQW
YMDNN
YMDNN : Date Code
Copyright
©
2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
IMONA
VDDIO
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
Marking Information
WQFN-40L 5x5
DS8179B-05 August 2016
RT8179B
Functional Pin Description
Pin No.
1, 33
2
4
3
5
6
7
8
9
10
11
12
Pin Name
BOOT,
BOOTA
TONSET
ISEN1P
ISEN1N
VSEN
FB
COMP
RGND
IMON
V064
IMONA
VDDIO
Pin Function
Bootstrap supply for high side MOSFET. This pin powers high side MOSFET
driver.
VDD controller on-time setting. Connect this pin to the converter input voltage,
VIN, through a resistor, R
TON
, to set the on-time of UGATE and also the output
voltage ripple of VDD controller.
Positive current sense input of Channel 1 for VDD controller.
Negative current sense input of Channel 1 for VDD controller.
VDD controller voltage sense input. This pin is connected to the terminal of
VDD controller output voltage.
Output voltage feedback input of VDD controller. This pin is the negative input
of the error amplifier for the VDD controller.
Error amplifier output pin of the VDD controller.
Return ground of VDD and VDDNB controller. This pin is the common negative
input of output voltage differential remote sense for VDD and VDDNB
controllers.
Current monitor output for the VDD controller. This pin outputs a voltage
proportional to the output current.
Fixed 0.64V output reference voltage output. This voltage is only used to offset
the output voltage of the IMON pin and the IMONA pin. Connect a 0.47F
capacitor from this pin to GND.
Current monitor output for the VDDNB controller. This pin outputs a voltage
proportional to the output current.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the SVI
pins.
System power good input. If PWROK is low, the SVI interface is disabled and
VR returns to BOOT-VID state with initial load-line slope and initial offset. If
PWROK is high, the SVI interface is running and the DAC decodes the
received serial VID codes to determine the output voltage.
Serial VID clock input from processor.
Serial VID data input from processor. This pin is a serial data line.
Serial VID telemetry input from VR. This pin is a push-pull output.
Over clocking offset setting for the VDD controller.
Over clocking offset setting for the VDDNB controller.
1st platform setting Pin. Platform can use this pin to set OCP_TDC threshold,
DVID compensation bit1 and internal ramp slew rate.
2st platform setting pin. Platform can use this pin to set quick response
threshold, OCP_TDC trigger delay time, DVID compensation bit0, VDDNB rail
zero load-line enable setting and over clocking offset enable setting.
Over current indicator for dual OCP mechanism. This pin is an open drain
output.
Controller power supply input. Connect this pin to 5V with a 1F or greater
ceramic capacitor for decoupling.
13
PWROK
14
15
16
17
18
19
20
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
21
22
OCP_L
VCC
Copyright
©
2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8179B-05 August 2016
www.richtek.com
3
RT8179B
Pin No.
23
24
25
26
27
28
29
30
31
32
34, 40
35, 39
36, 38
37
41 (Exposed Pad)
Pin Name
IBIAS
COMPA
FBA
VSENA
ISENA1N
ISENA1P
EN
PGOODA
PGOOD
TONSETA
UGATEA
UGATE,
PHASEA
PHASE,
LGATEA
LGATE,
PVCC
GND
Pin Function
Internal bias current setting. Connect only a 100k resistor from this pin to
GND to generate bias current for internal circuit. Place this resistor as close to
IBIAS pin as possible.
Error amplifier output of the VDDNB controller.
Output voltage feedback input of VDDNB controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
VDDNB controller voltage sense input. This pin is connected to the terminal of
VDDNB controller output voltage.
Negative current sense input of Channel 1 for VDDNB controller.
Positive current sense input of Channel 1 for VDDNB controller.
Controller enable pin. A logic high signal enables the controller.
Power good indicator for the VDDNB controller. This pin is an open drain
output.
Power good indicator for the VDD controller. This pin is an open drain output.
VDDNB controller on-time setting. Connect this pin to the converter input
voltage, VIN, through a resistor, R
TONNB
, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
Upper gate driver outputs. Connect this pin to Gate of high side MOSFET.
Switch nodes of high side driver. Connect this pin to high side MOSFET
Source together with the low side MOSFET Drain and the inductor.
Lower gate driver outputs. This pin drives the gate of low side MOSFET.
Driver power. Connect this pin to GND by ceramic capacitor larger than 1F.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Copyright
©
2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS8179B-05 August 2016
RT8179B
Functional Block Diagram
SVC
PGOODA
PWROK
PGOOD
VSEN
VSENA
OCP_L
OFSA
SET1
SET2
VDDIO
VCC
OFS
SVD
SVT
IMONI
IMONAI
EN
UVLO
GND
MUX
ADC
IBIAS
From Control Logic
RGND
DAC
VSETA
ERROR
AMP
+
-
SVI2 Interface
Configuration Registers
Control Logic
OFS/OFSA
Load Line
/Load Line A
RSET/RSETA
OCP Threshold
Loop Control
Protection Logic
TONSETA
Soft-Start & Slew
Rate Control
FBA
COMPA
ISENA1P
ISENA1N
Offset
Cancellation
+
+
-
PWM
CMPA
QRA
TONA
TON
GENA PWMA
1-PH
Driver
BOOTA
UGATEA
PHASEA
LGATEA
Current mirror
+
x2
-
IBA1
V064
+
0.4
-
RSETA
Average
IMONAI
Driver
POR
To Protection Logic
OV/UV/NV
TONSET
BOOT
Offset
Cancellation
+
IMONA
From Control Logic
RGND
DAC
Soft-Start & Slew Rate
Control
VSET
ERROR
AMP
+
-
PVCC
OCP_TDCA,
OCP_SPIKEA
+
-
OCA
VSENA
PWM1
QR
TON
TON
GEN
FB
COMP
1-PH
Driver
UGATE
PHASE
LGATE
+
Current mirror
ISEN1P
ISEN1N
+
x1
-
-
PWM
CMP
IB1
+
0.4
-
RSET
Average
+
-
IMONI
OC
OCP_TDC,
OCP_SPIKE
To Protection Logic
OV/UV/NV
VSEN
IMON V064
Copyright
©
2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8179B-05 August 2016
www.richtek.com
5
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