LLP
Link Layer Processor
Product Brief, Revision 1
Introduction
The Link Layer Processor (LLP) offers a highly integrated
solution for multiservice applications such as wireline ac-
cess network and 2.5G/3G wireless access applications.
The full bidirectional data bandwidth of the LLP can be
used entirely by a single protocol path or can be simulta-
neously partitioned among the three protocol paths, al-
lowing migration from circuit switching (TDM) to cell
switching (ATM) to packet switching (IP) on a common
platform.
The LLP device supports multichannel ATM transmis-
sion convergence (TC), inverse multiplexing for ATM
(IMA), ATM adaptation layer type 1 segmentation and re-
assembly (AAL1 SAR), multichannel high-level data link
control (HDLC), and multilink/multiclass point-to-point
protocol (ML/MC/PPP) data-link layer functions. These
protocols are processed between DS1/E1/J1 links and
industry standard system interfaces (SPI-3,
POS-PHY™
Level 2 or UTOPIA-2).
All device features described in this product brief are fully
accessible through an Agere Systems supplied software
package.
AAL1 SAR processing:
— Up to 672 virtual circuits (VCs).
— Supports both structured data transfer (SDT mode)
and unstructured data transfer (UDT) modes.
— Clock recovery for adaptive clocking scheme.
— Channel associated signaling (SDT mode).
— Partial fill of ATM cells (SDT mode).
ML/MC/PPP HDLC processing:
— HDLC framing and deframing for up to 672 HDLC
channels (transmit and receive, 56 kbits/s to
2.048 Mbits/s data rate per HDLC channel).
— Up to 128 PPP channels on any of up to 84 links,
84 ML PPP bundles, bundle sizes from
1—128 PPP channels.
— ML/MC/PPP support for up to 16 classes.
— Simultaneous processing for various packet types:
generic, PPP, ML/PPP, and ML/MC/PPP.
— Packet size up to 9600 bytes.
Subrate HDLC processing:
— Insertion and extraction for up to 64 subrate
(8 kbits/s to 64 kbits/s rate) HDLC channels.
Frame relay support:
— The LLP provides up to 672 HDLC terminations.
Transcoder rate adapter unit (TRAU) frame support:
— Up to 940 TRAU channels with inband messaging.
— Supports mappings of full-rate (FR), half-rate (HR),
and adaptive multirate (AMR HR) speech into
TRAU frames.
516-pin PBGA package (31 mm x 31 mm).
Features
Line interfaces:
— Up to 155 Mbits/s bidirectional bandwidth through
channelized OC-3/STM-1:
Up to three NSMI ports (51.84 Mbits/s each) sup-
porting up to 84 DS1/J1 links or 63 E1 links.
— Supports up to 16 LIU ports with internal framer.
— Four synchronous CHI ports for direct TDM inter-
face to time-slot interchanger (TSI) devices.
8-bit SPI-3 (system packet interface Level 3),
8-bit/16-bit UTOPIA Level 2, or 8-bit/16-bit
POS-PHY
Level 2, multi-PHY slave system interface.
Embedded shared RAM for storage of payload and
control structures with optional 16-bit DDR SDRAM
interface for external memory expansion.
Fractional DS1/J1/E1 logical channel mapping to
each of the three protocol processing paths.
Line side NxDS0 cross connect via AAL0/1
ATM protocol processing for TC/IMA:
— Support for any combination of up to 84 IMA groups
or UNI links with fractional support.
— From 1 to 32 links per IMA group.
Product Brief
www.agere.com
August 3, 2006
Link Layer Processor (LLP)
Product Brief, Revision 1
August 3, 2006
LLP Block Diagram
DDR SDRAM
46
External Memory Interface
Embedded Shared RAM
(x3) NSMI
21
AAL1
System
Interface
SPI-3
POS-PHY
L2
UTOPIA-2
75
(x16) Line Interface
(x28 Tx Clk)
108
TC
Line
Interface
Framer
HDLC
IMA
Line Encoder/
Decoder
System
Interface
(x4) CHI
12
ML/MC/PPP
Embedded Device Controller (EDC)
31
JTAG
5
Host Interface
42
4
JTAG IF
Test/GPIO
Power and GND pins not shown
Host IF
Clocks and Reset
Applications
Media gateways, routers, RNCs, pseudo wire applications
Ordering Information
Below is the ordering information for one product in the family. Please refer to the
LLP Family Selection Guide
for other
products that are available in this same family.
Table 1. Ordering Information
Device
LLP16084
Part Number
LLP1608421BL1-DB
L-LLP16018421BL1-DB
Package
516 PBGAM1T
516 PBGAM1T
Comcode
711010275
711010276
Note:
Part numbers beginning with L- are RoHS compliant.
For additional information, contact your Agere Systems Account Manager, sales at www.agere.com/sales, or email us at docmaster@agere.com.
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere
Systems, and the Agere logo are registered trademarks of Agere Systems Inc.
POS-PHY
is a registered trademark of PMC Sierra, Inc.
Copyright © 2006 Agere Systems Inc. All Rights Reserved.
August 3, 2006
PB05-027MPIC-1 (Replaces PB05-027MPIC)
微控制器 MCU
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