HT6P20X Series
2
24
OTP Encoder
Features
·
Operating voltage: 2V~12V
·
Low power consumption
·
Built-in oscillator needs only 5% resistor
·
0/2/4/8 data selectable
·
2
24
·
One time programmable process
·
Data active: D0~D7
·
Minimal external components
·
HT6P20A/B: 8-pin DIP/SOP package
maximum address and data codes
HT6P20D: 16-pin DIP/NSOP package
·
Easy interface with an RF or IR medium
Applications
·
Burglar alarm system
·
Smoke and fire alarm system
·
Garage door controllers
·
Car door controllers
·
Security system
·
Cordless telephones
·
Other remote control systems
General Description
The HT6P20X is a CMOS LSI encoder designed for re-
mote control system applications. It encodes 24 bits of
information and then serially transmits it via the DOUT
pin upon receipt of transmission enable (DATA pins:
D0~D7) signals. The combination of address and data
bits of the HT6P20X is designed using one time pro-
grammable process. In addition, the chip offers various
packaging for flexible combination of programmable ad-
dress/data so as to meet various applications. Its pro-
grammable address/data is transmitted together with
the anti-code bits via RF or infrared transmission me-
dium upon receipt of a trigger signal.
Block Diagram
O S C 1
O S C 2
V P P
S IO
O s c illa to r
A d d re s s
C o u n te r
P r o g r a m m in g
C ir c u it
M ix e r &
D r iv e r
D O U T
C o n tr o l U n it
D a ta L a tc h
P G M
D 0
D 7
Note: Address/Data numbers are available in various combinations, refer to the functional description.
Rev. 1.40
1
June 20, 2003
HT6P20X Series
Pin Assignment
2 4 -A d d re s s
0 -D a ta
2 2 -A d d re s s
2 -D a ta
2 0 -A d d re s s
4 -D a ta
D 1
1
2
3
4
5
6
7
8
D 2
D 3
V S S
P G M
1
8
2
7
3
6
4
5
V S S
O S C 2
O S C 1
S IO
V P P
V D D
D O U T
D 0
1
8
2
7
3
6
4
5
D 1
V S S
O S C 2
N C
V D D
D O U T
O S C 1
N C
N C
N C
N C
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
D 0
P G M
S IO
V P P
V D D
D O U T
O S C 1
O S C 2
H T 6 P 2 0 A
8 D IP /S O P
H T 6 P 2 0 B
8 D IP /S O P
H T 6 P 2 0 D
1 6 D IP /N S O P
Pin Description
HT6P20D
Pin No.
16
1~3
4
5~8
9
10
11
12
13
14
15
Pin Name
D0~D3
VSS
NC
OSC2
OSC1
DOUT
VDD
VPP
SIO
PGM
I/O
I
¾
¾
O
I
O
¾
I
I/O
I
Internal
Connection
CMOS IN
Pull-high
¾
¾
OSCILLATOR
OSCILLATOR
CMOS OUT
¾
¾
CMOS
IN/OUT
CMOS IN
Pull-high
Description
Data input and transmission enable (active low)
They can be externally set to VSS or left open.
Negative power supply, ground
No connection
Oscillator output pin
Oscillator input pin
Data serial transmission output
Positive power supply
Programming power supply, V
DD
for normal operation
Programming address/control code input and mode code output for
mode verification
Program mode control pin, active low
Approximate internal connection circuits
C M O S IN
P u ll- h ig h
V
D D
C M O S IN /O U T
C M O S O U T
O S C IL L A T O R
O S C 1
O S C 2
Rev. 1.40
2
June 20, 2003
HT6P20X Series
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+12V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-20°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Electrical Characteristics
Symbol
V
DD
I
STB
I
DD
V
IH
V
IL
R
PH
Parameter
Operating Voltage
Standby Current
Operating Current
²H²
Input Voltage
²L²
Input Voltage
D0~D7 Pull-high Resistance
Source
12V
I
DOUT
Output Current
5V
Sink
12V
f
OSC
Oscillator Frequency
12V
0.1V
DD
R
OSC
=1.4MW
6
¾
15
3
0.1V
DD
0.9V
DD
Test Conditions
V
DD
¾
12V
12V
¾
¾
12V
5V
0.9V
DD
Conditions
¾
Oscillator stops
No load, f
OSC
=3kHz
¾
¾
¾
Min.
2
¾
¾
0.8V
DD
0
¾
-2
-6.5
2
Typ.
¾
1
200
¾
¾
150
-5
-15
5
Max.
12
2
400
V
DD
0.2V
DD
300
¾
¾
¾
¾
¾
Ta=25°C
Unit
V
mA
mA
V
V
kW
mA
mA
mA
mA
kHz
Functional Description
Normal Operation
The HT6P20X encodes and transmits address/data to a decoder upon receipt of a trigger signal. The address codes of
the HT6P20A are always transmitted as long as power (VDD) is supplied. The transmission function of the HT6P20B/D
is enabled by the D0~D7 pins (active low). The following is the transmission timing of the HT6P20X:
D 0 ~ D 7
< 1 w o rd
E n c o d e r
D O U T
> 1 w o rd
Transmission timing
A complete code word of the HT6P20D consists of 3 periods as shown below.
fo s c
D O U T
1 c lo c k
1 /3 b it
p ilo t p e r io d
( 2 3 c lo c k s )
( A 0 ~ A 1 9 , 6 0 c lo c k s )
a d d r e s s c o d e p e r io d
( D 3 ~ D 0 , 1 2 c lo c k s )
d a ta c o d e p e r io d
0
1
0
1
a n ti- c o d e p e r io d
( 4 b its )
A complete code word for the HT6P20D
Rev. 1.40
3
June 20, 2003
HT6P20X Series
The HT6P20A/B/D detects the logic state of the internal programmed address and the external data pins, and then trans-
mits the detected information during the code period. Each address/data bit can be set to one of the following two logic
states:
fo s c
" O n e "
"Z e ro "
A d d re s s /
D a ta b it
Flowchart
P o w e r o n
S ta n d b y m o d e
N o
N o
T r a n s m is s io n
e n a b le d ?
Y e s
A d d re s s /d a ta w o rd s
tr a n s m itte d
N o
P G M = 0 ?
Y e s
P r o g r a m m in g
m o d e
P r o g r a m m in g
c o m p le te d ?
Y e s
N o
T r a n s m is s io n
s till e n a b le d
Y e s
A d d re s s /d a ta w o rd s
tr a n s m itte d
c o n tin u o u s ly
N o te : O n e tim e p r o g r a m m a b le
Rev. 1.40
4
June 20, 2003
HT6P20X Series
Application Circuits
T r a n s m itte r C ir c u it
T r a n s m itte r C ir c u it
1
2
1
2
3
R o s c
4
P G M
V S S
O S C 2
O S C 1
S IO
V P P
V D D
D O U T
6
T E
5
L E D
8
7
7
8
4
+ 1 2 V
6
5
3
D 1
D 2
D 3
V S S
N C
N C
N C
N C
D 0
P G M
S IO
V P P
V D D
D O U T
O S C 1
O S C 2
9
1 6
1 5
1 4
1 3
1 2
1 1
1 0
R o s c
L E D
+ 1 2 V
H T 6 P 2 0 A
R o s c
@
1 .4 M
W
H T 6 P 2 0 D
R o s c
@
1 .4 M
W
T r a n s m itte r C ir c u it
1
2
3
4
5
6
7
8
D 1
D 2
D 3
V S S
N C
N C
N C
N C
D 0
P G M
S IO
V P P
V D D
D O U T
O S C 1
O S C 2
9
1 6
1 5
1 4
1 3
1 2
1 1
1 0
R o s c
+ 1 2 V
1 0 0
W
0 .1
m
.
H T 6 P 2 0 D
R o s c
@
1 .4 M
W
Rev. 1.40
5
June 20, 2003
FPGA/CPLD
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