IS41LV16100D
1Mx16
16Mb DRAM WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
—
Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode: 1,024 cycles /128 ms
• JEDEC standard pinout
• Single power supply:
3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range: -40
o
C to +85
o
C
PRELIMINARY INFORMATION
MARCH 2016
DESCRIPTION
The ISSI IS41LV16100D is a 1,048,576 x 16-bit high-
performance CMOS Dynamic Random Access Memories.
These devices offer a cycle access called Extended Data
Out (EDO) Page Mode. EDO Page Mode allows 1,024
random accesses within a single row with access cycle
time as short as 30 ns per 16-bit word. It is asynchronous,
as it does not require a clock signal input to synchronize
commands and I/O.
These features make the IS41LV16100D ideally suited
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications that run without a clock to synchronize with
the DRAM.
The IS41LV16100D is packaged in a 42-pin 400-mil SOJ
and 400-mil 50/44 pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
Max.
RAS Access Time (t
rac
)
Max.
CAS Access Time (t
cac
)
Max. Column Address Access Time (t
aa
)
Min. EDO Page Mode Cycle Time (t
pc
)
Min. Read/Write Cycle Time (t
rc
)
-50
50
14
25
30
85
Unit
ns
ns
ns
ns
ns
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 0A
3/29/2016
1
IS41LV16100D
Functional Description
The IS41LV16100D is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column Ad-
dress Strobe (CAS).
RAS
is used to latch the first nine bits
and
CAS
is used to latch the latter nine bits.
The IS41LV16100D has two
CAS
controls,
LCAS
and
UCAS.
The LCAS and
UCAS
inputs internally generates a
CAS
signal
functioning in an identical manner to the single
CAS
input on
the other 1M x 16 DRAMs. The key difference is that each CAS
controls its corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41LV16100D CAS function is determined by the
first
CAS
(LCAS or
UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16100D BYTE READ and BYTE WRITE cycle
capabilities.
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding
RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving
RAS
HIGH for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the
RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst
refresh sequence, all 1,024 rows must be refreshed within
the average internal refresh rate, prior to the resumption
of normal operation.
Memory Cycle
A memory cycle is initiated by bring
RAS LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
ras
time has expired. A new cycle
must not be initiated until the minimum precharge time
t
rp
, t
cp
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE HIGH.
The column
address must be held for a minimum time specified by t
ar
.
Data Out becomes valid only when t
rac
, t
aa
, t
cac
and t
oea
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function,
the
CAS
cycle time can be shorter than in the fast page
mode if the timing margin is the same.
The EDO page mode allows both read and write operations
during one
RAS
cycle, but the performance is equivalent
to that of the fast page mode in that case.
Power-On
During Power-On,
RAS, UCAS, LCAS,
and
WE
must
all track with V
dd
(HIGH) to avoid current surges,
and allow initialization to continue. An initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
5
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through
A9) with
RAS
at least once every t
ref
max. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the addressed
row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS LOW. In CAS-before-RAS
refresh cycle,
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
3/29/2016
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
