Data Sheet
January 2000
1340-Type Lightwave Receiver
s
s
s
CMOS (TTL) link-status flag output
Operation at 1.3
µ
m or 1.55
µ
m wavelengths
Operating case temperature range of
–40
°
C to +85
°
C
x13
40
622
MB
Applications
s
Telecommunications
— Inter- and intraoffice SONET/ITU-T SDH
— Subscriber loop
— Metropolitan area networks
High-speed data communications
s
Operating at 1.1
µ
m through 1.6
µ
m wavelengths and at
155 Mbits/s, 622 Mbits/s, or 1.25 Gbits/s, the versatile
1340-Type Receiver is manufactured in a 20-pin, plastic DIP
with a multimode fiber pigtail.
Description
The 1340-Type receiver is designed for use in trans-
mission systems or medium- to high-speed data
communications applications at data rates up to
1.25 Gbits/s. Compact packaging, along with wide
dynamic range, makes these receivers ideal for both
telecommunications and data communications appli-
cations.
The following three versions of the receiver are avail-
able:
s
s
s
Features
s
s
s
s
Backward compatible with 1310 receiver family
Space-saving, self-contained, 20-pin plastic DIP
Silicon based ICs
Single 5 V power supply operation including photo-
current monitor capability
Exceeds all SONET (GR-253-CORE) and ITU-T
G.958 jitter requirements
Wide dynamic range
Qualified to meet the intent of
Telcordia Technolo-
gies
* reliability practices
Operates at data rates of 155 Mbits/s,
622 Mbits/s, or 1.25 Gbits/s
Positive ECL (PECL) data outputs
s
SONET/SDH compliant with OC-3/STM-1
SONET/SDH compliant with OC-12/STM-4
1.25 Gbits for data applications.
s
s
*
Telcordia Technologies
is a trademark of Bell Communications
Research, Inc.
s
s
1340-Type Lightwave Receiver
Data Sheet
January 2000
signal amplification, data threshold detection, and
PECL data outputs. The incoming optical signal is cou-
pled into the receiver through a 62.5
µ
m core multi-
mode fiber pigtail. The outer jacket diameter of the
pigtail is 900
µm.
The receiver can be ordered with the
pigtail terminated in an FC/PC, SC, or
ST
®
optical con-
nector. Other connectors are available on special order.
See your Lucent account representative for ordering
conditions and information.
The receiver has differential PECL data outputs and,
depending on the version selected, either differential
PECL link status flag or complementary CMOS link
status flag outputs. The link status flag outputs indicate
the presence or absence of a minimum acceptable
level of optical input signal.
Description
(continued)
The SONET/SDH versions of the receiver are fully
compliant with the latest issue of
Telcordia Technolo-
gies
GR-253- CORE and the most recent issues of ITU
recommendations G.957 and G.958. The 1340-Type
receiver requires only a single 5 V power supply for
operation. All versions of the receiver are characterized
for operation over the case operating range of –40
°C
to +85
°C
at the appropriate data rate for each version.
Manufactured in a 20-pin DIP, the receivers use a pla-
nar, rear illuminated InGaAs PIN photodetector that
allows these receivers to be used at wavelengths from
1.1
µm
to 1.6
µm.
The photocurrent output of the PIN
detector is amplified and converted to a voltage by a
silicon amplifier. A silicon quantizer provides additional
V
CC
FLAG
FLAG
FILTER
InGaAs
PIN
Si
PREAMPLIFIER
Si
COMPARATOR
FILTER
OPTIONAL
V
PIN
DATA
DATA
1-414(C)
Figure 1. Block Diagram
2
Lucent Technologies Inc.
Data Sheet
January 2000
1340-Type Lightwave Receiver
Description
(continued)
To help ensure high product reliability and customer
satisfaction, Lucent is committed to an intensive quality
program that starts in the design phase and proceeds
through the manufacturing and shipping process. Opto-
electronics subsystems are qualified to Lucent internal
standards using MIL-STD-883 test methods and pro-
cedures and sampling techniques consistent with
Tel-
cordia Technologies
requirements. The 1340 receiver
qualification program meets the intent of
Telcordia
Technologies
TR-NWT-000468 and TA-TSY-000983.
Application Information
The 1340 receiver is a highly sensitive fiber-optic
receiver. Although the data outputs are digital logic lev-
els (PECL), the device should be thought of as an ana-
log component. When laying out the printed-wiring
board (PWB), the 1340 receiver should be given the
same type of consideration one would give to a sensi-
tive analog component.
At a minimum, a double-sided printed-wiring board with
a large component-side ground plane beneath the
receiver must be used. In applications that include
many other high-speed devices, a multilayer PWB is
highly recommended. This permits the placement of
power and ground connections on separate layers,
which helps minimize the coupling of unwanted signal
noise into the power supplies of the receiver.
Noise that couples into the receiver through the power
supply pins can also degrade device performance. The
application schematics, Figures 3—5, show recom-
mended power supply filtering that helps minimize
noise coupling into the receiver. The bypass capacitors
should be high-quality ceramic devices rated for RF
applications. They should be surface-mount compo-
nents placed as close as possible to the receiver power
supply pins. The ferrite bead should have as high an
impedance as possible in the frequency range that is
most likely to cause problems. This will vary for each
application and is dependent on the signaling frequen-
cies present on the application circuit card. Surface-
mount, high-impedance beads are available from sev-
eral manufacturers.
Data and Flag Outputs
The data outputs of the 1340 receiver are driven by
open-emitter NPN transistors which have an output
impedance of approximately 7
Ω
. Each output can pro-
vide approximately 50 mA maximum output current.
Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (DATA and DATA) should be terminated
identically. The signal lines connecting the data outputs
to the next device should be equal in length and should
have matched impedances.
Controlled impedance stripline or microstrip construc-
tion must be used to preserve the quality of the signal
into the next component and to minimize reflections
back into the receiver. Excessive ringing due to reflec-
tions caused by improperly terminated signal lines
makes it difficult for the component receiving these sig-
nals to decipher the proper logic levels and may cause
transitions to occur where none were intended. Also, by
minimizing high frequency ringing due to reflections
caused by improperly designed and terminated signal
lines, possible EMI problems can be avoided. The
applications sections in the Signetics
*
ECL 10K/100K
Data Manual or the National Semiconductor
†
ECL
Logic Databook and Design Guide
provide excellent
design information on ECL interfacing.
Layout Considerations
A fiber-optic receiver employs a very high-gain, wide-
bandwidth transimpedance amplifier. The amplifier
detects and amplifies signals that are only tens of nA in
amplitude. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver’s sensitivity and can also degrade the perfor-
mance of the receiver’s loss of signal (FLAG) circuit.
To minimize the coupling of unwanted noise into the
receiver, route high-level, high-speed signals such as
transmitter inputs and clock lines as far away as possi-
ble from the receiver pins. If this is not possible, then
the PWB layout engineer should consider interleaving
the receiver signal and flag traces with ground traces in
order to provide the required isolation.
*
Signetics
is a registered trademark of Signetics Corp.
†
National Semiconductor
is a registered trademark of National
Semiconductor Corporation.
Lucent Technologies Inc.
3
1340-Type Lightwave Receiver
Data Sheet
January 2000
output signal. The outputs of the LT1016 are TTL-com-
patible and provide both true and inverted logic levels.
The Q output of this circuit will be a TTL high (>2.5 V)
when the 1340 is receiving an optical signal greater
than the FLAG switching threshold and will be a TTL
low (<0.4 V) whenever the optical signal is absent or is
below the FLAG switching threshold. The FLAG and
FLAG outputs of the OC-12/STM-4 and 1.25 Gbits/s
receivers are 5 V TTL logic level compatible. The FLAG
output is provided directly by the comparator IC. How-
ever, the FLAG output is derived from the FLAG output
through an inverter. Excessive loading of the FLAG out-
put can cause the FLAG output to malfunction.
Data and Flag Outputs
(continued)
The FLAG and FLAG outputs of the OC-3/STM-1
155 Mbits/s version of the 1340 receiver are PECL
logic levels driven by open emitter transistors with the
same characteristics as the data outputs. These out-
puts must be properly terminated in order to obtain the
correct logic levels. Since the FLAG function is basi-
cally a dc switch that indicates the loss of optical input
signal, it can be interfaced to much slower TTL or
CMOS logic circuits.
The circuit shown in Figure 2 provides one example of
how to create a TTL logic output from the PECL FLAG
+5 V
+5 V
11
1340
R
X
FLAG
FLAG
12
14
+
LT1016*
–
Q
TTL (INVERTED)
Q
TTL (TRUE)
10 kΩ
10 kΩ
1-800(C).a
* Part available from Linear Technology Corporation of Milpitas, CA 95035.
Figure 2. Converting PECL FLAG Outputs to TTL
4
Lucent Technologies Inc.
Data Sheet
January 2000
1340-Type Lightwave Receiver
A single 50
Ω
resistor terminated to (V
CC
– 2 V) could
also be used, but this requires a second power supply.
Other methods of terminating ECL-type outputs are
discussed in the references previously mentioned.
Figure 5 shows an example of a circuit that can be
used to interface the PECL outputs of the 1340
receiver with a device which requires true, negative
voltage ECL inputs. The 100314 is an ECL line receiver
and is shown here only as an example to demonstrate
this coupling procedure. The DATA lines are terminated
in a 50
Ω
equivalent impedance but are ac-coupled to
the 100314. The capacitive coupling isolates and per-
mits level shifting of the positive DATA outputs of the
receiver to the proper negative level required by the
inputs of the 100314. The V
BB
output of the 100314
provides the reference voltage required to center the
voltage swing of the DATA signals around the input
switching threshold of the 100314. The Thévenin
equivalent of the 166
Ω
and 250
Ω
resistor pair is
100
Ω
, which, in parallel with the 100
Ω
resistor con-
nected to V
BB
, results in a 50
Ω
equivalent impedance
for the load on each of the data lines. Alternatively, if
there is no V
BB
reference available, a second pair of
166
Ω
/250
Ω
resistor networks could be used on the
data lines on the 100314 side of the coupling capacitor.
Pin 10
Pin 10 on the 1340-Type receiver is a not internally
connected (NIC) pin. This definition allows the 1340 to
be used in most customer 20-pin receiver module
applications. Customer’s printed-wiring boards that are
designed with ground, +5 V, –5 V, or no connection to
this pin are all acceptable options. For those applica-
tions that require monitoring the photocurrent of the
PIN photodetector for power monitoring purposes,
there are versions of the 1340 that require +5 V or –5 V
applied to Pin 10. Check Tables 4 and 5 for ordering
information.
Recommended User Interface
The 1340 receiver is designed to be operated from a
5 V power supply and provides raised or pseudo-ECL
(PECL) data outputs. Figures 3 and 4 show two possi-
ble application circuits for the 1340 receiver. Figure 3
represents an application for the version with PECL
FLAG outputs while Figure 4 shows a possible applica-
tion for the version with the TTL-compatible FLAG
outputs.
In both instances, the DATA outputs are terminated with
a Thévenin equivalent circuit, which provides the equiv-
alent of a 50
Ω
load terminated to (V
CC
– 2 V).
+5.0 V
2.2 µF
†
FERRITE
BEAD
‡
0.1 µF
82
Ω
FLAG*
FLAG*
124
Ω
124
Ω
82
Ω
0.1 µF
11
12
1340
14
7
9
0.1 µF
82
Ω
82
Ω
0.1 µF
DATA
†
DATA
†
124
Ω
124
Ω
* 50
Ω
to (V
CC
– 2) V.
† DATA and
DATA
are 50
Ω
impedance transmission lines; both lines can be ac- or dc-coupled into the next device.
‡ Fair-Rite Products Corporation part number 2743037447 or equivalent.
Note: All unused outputs must be terminated as shown. All resistors are 1/8 W, thin-film, ceramic chips. All capacitors are
25 Vdc, ceramic X7R, or equivalent.
1-500(C).d
Figure 3. Interfacing to the 155 Mbits/s 1340 Receiver
Lucent Technologies Inc.
5
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