Dual-VCXO/Triple-PLL Programmable Clock Generator IC
1.0
•
•
•
•
•
•
Features
2.0
Description
Two voltage-controlled crystal oscillators (VCXO)
Three fully programmable phase-locked loops (PLL)
Three system clock frequency outputs
I C
ä
-bus serial interface
2
3.3 volt operation (contact factory for 5 volt versions)
Compact 16-pin SOIC (0.150”) package
Figure 1: Pin Configuration
XAO
XAI
XTUNEA
SCL
SDA
VDD
ADDR
VSS
1
2
3
16
15
14
XBO
XBI
XTUNEB
VSS
CLKC
VDD
CLKB
CLKA
4
5
6
7
8
13
12
11
10
9
The FS6219 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video / audio systems.
Two fully independent VCXOs permit accurate and
simulaneous phase locking of the generated clocks to
independent sources, such as satellite or cable delivered
video and terrestrial broadcasts.
Three fully independent, fully programmable PLLs with
flexible post-dividers permit the generation of desired
clock frequencies precisely, with no added “synthesis”
errors.
The FS6219 makes use of the latest AMI PLL technology
for low clock period jitter and low cumulative jitter.
The ADDR pin permits two FS6219 to be uniquely con-
2
trolled by a single I C bus. The full read/write slave
capability of the FS6219 allows all device programming to
be completely verified.
Contact factory for custom requirements.
Figure 2: Device Block Diagram
XTUNEA
XAI
CLKA
Crystal
Oscillator
XAO
"A"
XBI
Crystal
Oscillator
XBO
"B"
XTUNEB
FPLLA
FPLLB
FPLLC
FS6219
FXA
PLL "A"
Post-Divider
"A"
FXB
Source
Select
PLL "B"
Source
Select
Post-Divider
"B"
Source
Select
CLKB
PLL "C"
FXA
Post-Divider
"C"
CLKC
SCL
SDA
I
2
C Interface
(Read / Write Slave)
FXB
FS6219
This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
2.28.02
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TYPE
AO
AI
AI
DI
U
NAME
XAO
XAI
XTUNEA
SCL
SDA
VDD
ADDR
VSS
CLKA
CLKB
VDD
CLKC
VSS
XTUNEB
XBI
XBO
Crystal Oscillator “A” Drive
Crystal Oscillator “A” Feedback
DESCRIPTION
Crystal Oscillator “A” Voltage Tuning Input
Serial Interface Clock Input
Serial Interface Data Input/Output
Power Supply (+3.3V nominal)
Serial Interface Address Select
Ground
Clock Output “A”
Clock Output “B”
Power Supply (+3.3V nominal)
Clock Output “C”
Ground
Crystal Oscillator “B” Voltage Tuning Input
Crystal Oscillator “B” Feedback
Crystal Oscillator “B” Drive
DI
U
O
P
DI
U
P
DO
DO
P
DO
P
AI
AI
AO
Note: When applying an external reference clock to the FS6219, it should be capacitively coupled to the XAO or XBO pins. The
XAI and/or XBI pins should be floating (no connection).
FS6219 VCXO Typical Characteristic
250
200
150
100
50
0
0
-50
-100
-150
-200
V(XTUNE) - volts
0.5
1
1.5
2
2.5
3
ISO9001
Deviation - ppm
2
2.28.02
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
3.0
Programming Information
Table 2: Register Map
(Note: All Register Bits are cleared to zero on power-up.)
ADDRESS
BYTE 15
BYTE 14
BYTE 13
BYTE 12
BYTE 11
BYTE 10
BYTE 9
BYTE 8
BYTE 7
BYTE 6
BYTE 5
BYTE 4
BYTE 3
BYTE 2
BYTE 1
BYTE 0
SRCPLL_A[1:0]
PDPLL_A
FBKDIV_A[7:3]
M-Counter
REFDIV_A[7:0]
SRCPLL_B[1:0]
PDPLL_B
FBKDIV_B[7:3]
M-Counter
REFDIV_B[7:0]
LFTC_A
CP_A
FBKDIV_A[10:8]
M-Counter
FBKDIV_A[2:0]
A-Counter
SRCPLL_C[1:0]
BIT 7
*
*
*
*
BIT 6
*
*
*
*
BIT 5
*
*
*
*
BIT 4
*
*
*
*
BIT 3
*
TSCLK_C
TSCLK_B
TSCLK_A
BIT 2
*
STOPCLK_C
STOPCLK_B
STOPCLK_A
BIT 1
*
BIT 0
*
SRCCLK_C[2:0]
SRCCLK_B[2:0]
SRCCLK_A[2:0]
SRCPOST_C[2:0]
SRCPOST_B[2:0]
SRCPOST_A[2:0]
MODPOST_C[3:0]
MODPOST_B[3:0]
MODPOST_A[3:0]
PDPLL_C
LFTC_C
CP_C
FBKDIV_C[7:3]
M-Counter
REFDIV_C[7:0]
LFTC_B
CP_B
FBKDIV_C[10:8]
M-Counter
FBKDIV_C[2:0]
A-Counter
FBKDIV_B[10:8]
M-Counter
FBKDIV_B[2:0]
A-Counter
3.1
Control Bit Assignment
Table 4: Divider Control Bits
NAME
REFDIV_x[7:0]
DESCRIPTION
REFerence DIVider for PLL “x” (N
R
)
FeedBacK DIVider for PLL “x” (N
F
)
FBKDIV_x[10:0]
FBKDIV_x[2:0]
FBKDIV_x[10:3]
A-Counter Value
M-Counter Value
If any PLL control bit is altered during device operation,
including those bits controlling the Reference and Feed-
back Dividers, the output frequency will slew smoothly (in
a glitch-free manner) to the new frequency. The slew rate
is related to the programmed charge pump current and
loop filter time constant.
However, any programming changes to any Mux or Post
Divider control bits will cause a glitch on an operating
clock output.
Table 5: Post-Divider Control Bits
NAME
MODPOST_x[3:0]
DESCRIPTION
Modulus for POST divider “x”
(see Table 7: Post Divider Modulus)
Table 3: PLL Power-Down Bits
NAME
DESCRIPTION
Power-Down PLL “x”
PDPLL_x
Bit = 0
Bit = 1
Power On
Power Off
Table 6: CLK Pin Stop Bit
NAME
DESCRIPTION
CLK “x” Stop Bit
STOPCLK_x
Bit=0
Bit=1
Normal, CLK running
CLK Stopped Low
ISO9001
3
2.28.02
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Table 7: Post Divider Modulus
BIT [3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BIT [2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BIT [1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BIT [0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIVIDE BY
1
2
3
4
5
6
8
9
10
12
15
16
18
20
25
50
Table 9: Post-Divider Source Select Bits
NAME
DESCRIPTION
Post-Divider “x” Reference Source Select
Bit[2]
0
SRCPOST_x
0
0
0
1
1
Bit[1]
0
0
1
1
0
1
Bit[0]
0
1
0
1
0
1
Reference Frequency A
Reference Frequency B
PLL A Frequency
PLL B Frequency
PLL C Frequency
Shutdown Post-Divider
Table 10: CLK Pin Source Select Bits
NAME
DESCRIPTION
CLK “x” Source Select
Bit[1]
SRCCLK_x
0
0
1
1
Bit[0]
0
1
0
1
Post-Divider “A”
Post-Divider “B”
Post-Divider “C”
TEST MODE
Table 8: PLL Reference Source Select Bits
NAME
DESCRIPTION
PLL “A” Reference Source Select
Bit[1]
SRCPLL_A
0
0
1
1
Bit[1]
SRCPLL_B
0
0
1
1
Bit[1]
SRCPLL_C
0
0
1
1
Bit[0]
0
1
0
1
Bit[0]
0
1
0
1
Bit[0]
0
1
0
1
Reference Frequency A
Reference Frequency B
PLL A Frequency
PLL B Frequency
Reference Frequency A
Reference Frequency B
PLL A Frequency
PLL C Frequency
LFTC_x
Reference Frequency A
Reference Frequency B
PLL B Frequency
PLL C Frequency
TSCLK_x
Table 11: CLK Pin Tri-State Bit
NAME
DESCRIPTION
CLK “x” Source Select
Bit=0
Bit=1
Normal, CLK enabled
CLK Tri-Stated
PLL “B” Reference Source Select
Table 12: PLL Tuning Bits
NAME
DESCRIPTION
Loop Filter Time Constant for PLL “x”
Bit = 0
Bit = 1
Time Constant = t.b.d.
Time Constant = t.b.d.
PLL “C” Reference Source Select
CP_x
Charge Pump Current for PLL”x”
Bit = 0
Bit = 1
Current = t.b.d.
Current = t.b.d.
ISO9001
4
2.28.02
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
4.0
Electrical Specifications
Table 13: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage (V
SS
= ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
V
SS
-0.5
-50
-50
-65
-55
MAX.
7
V
DD
+0.5
V
DD
+0.5
50
50
150
125
125
260
2
UNITS
V
V
V
mA
mA
°C
°C
°C
°C
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
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