Device Configurations and Pin-outs ............................................................................................................................................. 6
Pin-out Top Views................................................................................................................................................................. 6
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ........................................................................................... 7
Frequency Stability ............................................................................................................................................................. 11
Output frequency and format .............................................................................................................................................. 11
Output Frequency Tuning ................................................................................................................................................... 11
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 12
Device Configurations and Design Considerations .................................................................................................................... 13
Control Voltage Bandwidth ................................................................................................................................................. 15
Pull Range, Absolute Pull Range ............................................................................................................................................... 16
I C Control Registers ................................................................................................................................................................. 21
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 21
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 22
Register Address: 0x02. DIGITAL PULL RANGE CONTROL ............................................................................................ 23
Register Address: 0x05. PULL-UP DRIVE STRENGTH CONTROL .................................................................................. 24
Register Address: 0x06. PULL-DOWN DRIVE STRENGTH CONTROL ............................................................................ 25
Serial Interface Configuration Description.................................................................................................................................. 26
Serial Signal Format .................................................................................................................................................................. 26
Parallel Signal Format................................................................................................................................................................ 27
Parallel Data Format .................................................................................................................................................................. 27
I C Timing Specification ............................................................................................................................................................. 29
I C Device Address Modes ........................................................................................................................................................ 30
Schematic Example ................................................................................................................................................................... 31
Dimensions and Patterns ........................................................................................................................................................... 32
Ordering Information .................................................................................................................................................................. 34
2
2
2
Rev 0.60
Page 2 of 36
www.sitime.com
SiT5356
1 to 60 MHz,
±0.1
to
±0.25
ppm
Elite Platform™ Precision Super-TCXO
Electrical Characteristics
PRELIMINARY
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3V Vdd
Table 1. Output Characteristics
Parameters
Output Frequency Range
Symbol
F
Min.
1
1
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Output Voltage Level
Frequency Stability over Temperature
DC
Tr, Tf
VOH
VOL
V_out
F_stab
45
–
90%
–
0.8
-0.1
Typ.
–
–
–
1
–
–
–
–
Max.
60
50
55
–
–
10%
1.2
+0.1
Unit
MHz
MHz
%
ns
Vdd
Vdd
V
ppm
10% - 90% Vdd
I
OH
= -6 mA, (Vdd = 3.3 V, 3.0 V, 2.8 V, 2.5 V)
I
OL
= 6 mA, (Vdd = 3.3 V, 3.0 V, 2.8 V, 2.5 V)
Measured peak-to-peak swing at any Vdd
Referenced to (max frequency + minimum
frequency)/2 over the rated temperature range, in
TCXO, DCTCXO or VCTCXO with ±6.25 ppm pull
mode
LVCMOS output
Clipped sinewave output
Condition
Frequency Coverage
LVCMOS Output Characteristics
Clipped Sinewave Output Characteristics
Frequency Stability - Stratum 3+ Grade
Frequency vs. Temperature Slope
Dynamic Frequency Change during
Temperature Ramp
Initial Tolerance
24-hour holdover stability
Hysteresis Over Temperature
ΔF/ΔT
F_dynamic
F_init
F_24_Hold
F_hys
–
–
-1
-0.28
–
–
–
–
–
–
–
–
–
-0.2
0.25
±2.5
±0.021
–
–
±15
±15
±10
±2.5
±1
±1
±3
±0.5
±1
–
–
±8
±0.07
–
–
–
+1
+0.28
–
–
–
–
–
–
–
–
–
+0.2
+0.25
–
–
+1
+0.32
ppb/°C
ppb/s
ppm
ppm
ppb
ppb
ppb
ppb
ppb
ppb
ppb
ppm
ppm
ppm
ppm
ppb/°C
ppb/s
ppm
ppm
ppb
ppb
ppb
ppb
ppm
ppm
ms
ms
0.5C/min temperature ramp rate
Initial frequency at 25°C inclusive of solder-down
shift at 48 hours after 2 reflows
Per Stratum 3 definition
Vdd ±5%
LVCMOS output, 15 pF ±10%
Clipped sinewave output, 10kΩ, 10 pF ±10%
After 30-days of continued operation
At 25°C
Stratum 3 per GR-1244
Time to first pulse, measured from the time Vdd
reaches 90% of its final value
Time to first accurate pulse within rated stability,
measured from the time Vdd reaches 90% of its final
value
0.5C/min temperature ramp rate
Initial frequency at 25°C inclusive of solder-down shift
at 48 hours after 2 reflows
Per Stratum 3 definition
-40 to 105C
-40 to 85C
-20 to 70C
Vdd ±5%
LVCMOS output, 15 pF ±10%
Clipped sinewave output, 10kΩ, 10 pF ±10%
After 30-days of continued operation
At 25°C
At 25°C
Referenced to (fmax + fmin)/2 over the rated
temperature range, in TCXO, DCTCXO or VCTCXO
with ±6.25 ppm pull mode
Supply Voltage Sensitivity
Output Load Sensitivity
One-Day Aging
One-Year Aging
20-Year Aging
Frequency Stability over Temperature
F_Vdd
F_load
F_1d
F_1y
F_20y
F_stab
Frequency Stability - Stratum 3 Grade
Frequency vs. Temperature Slope
Dynamic Frequency Change during
Temperature Ramp
Initial Tolerance
24-hour holdover
Supply Voltage Sensitivity
Output Load Sensitivity
One-Day Aging
One-Year Aging
20-Year Total Stability
Start-up Time
First Pulse Accuracy
ΔF/ΔT
F_dynamic
F_init
F_24_Hold
F_Vdd
F_load
F_1d
F_1y
F_20y
T
T_start
T_stability
–
–
-1
-0.32
–
–
–
–
–
-4.6
–
–
±2.5
±2
±1
±3
±1
–
5
10
–
–
–
–
–
+4.6
–
–
Start-up Characteristics
Rev 0.60
Page 3 of 36
www.sitime.com
SiT5356
1 to 60 MHz,
±0.1
to
±0.25
ppm
Elite Platform™ Precision Super-TCXO
Table 2. DC Characteristics
Parameters
Supply Voltage
Symbol
Vdd
Min.
2.25
2.52
2.7
2.97
Current Consumption
OE Disable Current
Operating Temperature Range
IDD
I_od
T_use
–
–
-20
-40
-40
Typ.
2.5
2.8
3.0
3.3
Max.
2.75
3.08
3.3
3.63
Unit
V
V
V
V
mA
mA
°C
°C
°C
PRELIMINARY
Condition
Contact
SiTime
for 2.25V to 3.63V continuous supply
voltage support
Supply Voltage
Current Consumption
–
40.5
40
–
–
–
–
Temperature Range
+70
+85
+105
F = 19.2 MHz, No Load
OE = GND, output is weakly pulled down
Extended commercial
Industrial
Extended Industrial
Table 3. Input Characteristics
Parameters
Input Impedance
Input High Voltage
Input Low Voltage
Pull Range
PR
Symbol
Z_in
VIH
VIL
Min.
–
70
–
Typ.
100
–
–
Max.
–
–
30
Unit
kΩ
%
%
2
Condition
Internal pull up to Vdd
Input Characteristics
–
OE Pin
Frequency Tuning Range – Voltage Control or I C mode
±6.25, ±10, ±12.5, ±25, ±50,
±80, ±100, ±125, ±150, ±200,
±400, ±600, ±800, ±1200,
±1600, ±3200
90%
–
10
–
Positive
–
2
ppm
Voltage Control Characteristics
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Frequency Change Polarity
Pull Range Linearity
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Current High
Leakage in high impedance mode
Input Hysteresis
Input Capacitance
Rise Time
Fall Time
VIL
VIH
VOL
IOL
I_leak
V_hys
C_in
Tr
Tf
VC_U
VC_L
VC_z
VC_c
–
–
–
10
0.5
–
–
–
–
–
–
–
–
–
–
–
–
10%
–
–
–
0.3
–
0.4
–
24
0.4
0.3
3
120
60
75
Vdd
Vdd
MΩ
kHz
%
V
V
V
mA
µA
V
V
pF
ns
ns
ns
Vdd = 3.3V, 30% to 70%
Vdd = 2.5V, 30% to 70%
0.1 Vdd< VOUT < 0.9 Vdd
Vdd = 3.3V
Vdd = 2.5V
Contact
SiTime
for other input bandwidth options
I C Interface Characteristics, 1 MHz, 200 Ohm, 550 pF (Max I
2
C Bus Load)
–
0.7
–
21
5.5
0.2
0.2
–
–
30
40
Rev 0.60
Page 4 of 36
www.sitime.com
SiT5356
1 to 60 MHz,
±0.1
to
±0.25
ppm
Elite Platform™ Precision Super-TCXO
Table 4. Jitter & Phase Noise
Parameters
RMS Phase Jitter (random)
Spurs
RMS Period Jitter
Peak Cycle-to-Cycle Jitter
1 Hz offset
10 Hz offset
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
T_jitt
T_jitt_cc
Symbol
Min.
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
0.35
0.33
-104
2
10
-70
-100
-130
-145
-152
-155
-162
-165
Max.
Jitter
T_phj
–
–
–
–
–
Phase Noise
–
–
–
–
–
–
–
–
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
dBc
ps
ps
Unit
PRELIMINARY
Condition
f = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
f = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz
f = 10 MHz, 12 kHz to 5 MHz offsets
f = 10 MHz per JESD65 standard
f = 10 MHz per JESD65 standard
f = 10 MHz, TCXO and DCTCXO modes, and VCTCXO
mode with ±6.25 ppm pull range
Table 5. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Continuous Power Supply Voltage Range (Vdd)
Human Body Model (HBM) ESD Protection
Soldering Temperature (follow standard Pb-free
soldering guidelines)
Junction Temperature
[1]
Note:
1. Exceeding this temperature for an extended period of time may damage the device.
中国 北京—— Analog Devices, Inc. （纽约证券交易所代码 : ADI ），全球领先的高性能信号处理解决方案供应商，最新推出两款模拟输出驱动器—— AD5750 和 AD5751 ，能显著提高过程控制应用的效率和可靠性，包括那些在高恒流电压和高温条件下工作的过程控制应用。这两款器件基于 ADI 公司的 iCMOS ™工业工艺技术，输出驱动器的精度...[详细]
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
