AMIS-50050:
Spread Spectrum Baseband Controller
Wireless Products
Data
Sheet
1.0 Introduction
AMI Semiconductor’s wireless product portfolio includes the AMIS-50050 spread spectrum baseband controller. AMI Semiconductor’s
AMIS-5005x products simplify the design of direct sequence spread spectrum radios. They contain all the baseband circuitry needed to
implement a radio, thus providing an economical solution to the extensive digital hardware requirements of high performance spread
spectrum radios. The AMIS-50050 is a low power device optimal for portable battery powered applications. It utilizes a 3.3V power
supply and interfaces to a 3V microprocessor and logic.
2.0 Key Features
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Low power with user controlled ‘shutdown’ modes
3.3V (+/-10 percent)
Narrow band and spread spectrum operation, independently selectable for transmit and receive
Performs all baseband functions required for implementation of direct sequence spread spectrum and can be used in any radio
frequency band
User programmable transmission protocol with pass through or packetization formatting
Generic microprocessor interface
Full or half duplex operation
High process gain (up to 2047chips/bit) with data rates from 100bps to 4Mbps
Independent transmit and receive PN code generators
Gold code and 11 -chip Barker code options
Programmable preamble lengths for faster acquisition when there has been recent transmission or reception
Byte-wide transmit and receive FIFOs
16 or 32 bit CRC error checking
8 or 16 bit receiver addressing
Optional data scrambling
Support for: binary phase shift keying (BPSK); differential binary phase shift keying (DBPSK); quadrature phase shift keying (QPSK);
differential quadrature phase shift keying (DQPSK)
Continuous tracking feature for transferring multiple packets of data at high data rates without reacquiring synchronized packet
The AMIS-50050 is a low power device optimal for portable battery powered applications. It utilizes a 3.3V power supply and interfaces
to a 3V microprocessor and logic.
The AMIS-50050 IC consists of a microprocessor interface and a full duplex transmit/receive message processor circuit. Included in the
AMIS-50050 message transmit processor circuits are the data scrambler, packet generator, CRC generator, pseudonoise (PN) code
generator, and modulation mode formatter. The AMIS-50050 message processor receive circuits include the receive PN code
generator, receive synchronization and tau-dither tracking loop, integrate and dump control, data descrambler, packet decoder, CRC
checker, demodulator, and signal strength indicator. Each transmit and receive PN code generator consists of two 11-bit PN
generators, allowing selection of an ‘A’ code, a “B” code, or a “Gold code” combination of the “A” and “B” codes. AMI Semiconductor’s
AMIS-50050 uses separate transmit and receive 64MHz VCOs, which allow fully independent transmit and receive operations.
AMI Semiconductor’s wireless ICs interface to a generic microprocessor bus for programming and data transfer and to an IF
modulator/demodulator and RF radio for the transmission medium. 8530 SCC operation and HDLC protocol are emulated for the
message packetization and error checking. No packetization can be selected for data to be transmitted as received from the host.
The AMIS-50050 is a high performance part, capable of chipping rates up to 64Mchips/second in transmit and receive modes. This
results in a maximum data rate of 2Mbps using QPSK or DQPSK modulation and a PN code length of 63. A maximum data rate of
1Mbps is achieved using BPSK or DBPSK modulation and a PN code length of 63. At lower chipping rates the ICs are capable of
generating code lengths up to 2047 chips. The lowest possible chipping rate is 300Hz. The flexibility of the design allows an optimal
combination of transmitted power, system process gain, system bandwidth and bit rate in order to achieve a reliable communication
channel with minimum interference to other adjacent channels or co-channel users.
AMI Semiconductor
– Sept. 06
www.amis.com
1
AMIS-50050:
Spread Spectrum Baseband Controller
Wireless Products
Data
Sheet
Table 3: Pin Descriptions
Pin Name
Type
AGND1
Analog GND
GND1
Ground
VDD1
Vdd
OSC1
OSC2
PLL[3:0]
TXD0
TXD1
EPOCH1
PN1
GND2
EXT[3:0]
VDD2
EXT[7:4]
EXT[9:8]
INT
RESET
CS
RD
WR
GND3
DATA[7:0]
ADDR[6:0]
VDD3
GND4
DUMP
EPOCH2
PN2
RCVRY
TEST
RXD1
RXD0
VREFD
AGND2
VCO2
AVDD2
DACOUT1
DACOUT0
RBIAS
VREF
AGND3
RSSI1
RSSI2
AVDD3
AVDD1
VCO1
Input
Padosc
Output
Output
Output
Output
Output
Ground
Output
Vdd
Output
Output
Output
Input
Input
Input
Input
Ground
BIDirection
Input
Vdd
Ground
Output
Output
Output
BIDirection
Input
Analog I/O
Analog In
Analog In
Analog GND
Analog Input
Analog VDD
Analog Output
Analog Output
Analog Input
Analog Input
Analog GND
Analog Input
Analog Input
Analog VDD
Analog VDD
Analog I/O
Functional Description
Crystal oscillator or external reference input, this input is divided by OSCDIV to generate the reference clock for
the transmit PLL
Xtal osc output
Off-chip PLL programming; Bit0, Enable1, Bit1; Sclk, Bit2, Enable0, Bit3, Sdata
Transmit data “I” output
Transmit data “Q” output, or QAM output clock
Transmit PN generator Epoch signal, (68 pin PLCC package only)
Transmit PN generator output, can be internally disabled (PMR Bit 4)
External control port (lower bits), user defined functions for radio control
External control port (upper bits), user defined functions for radio control
External control port (upper bits), user defined functions for radio control (68 pin PLCC package only)
Active high – initiates an interrupt to the microprocessor
Active low – sets all registers to standby states
Active low – selects the chip for reading and writing via the µP interface
Active low – initiates a read operation via the µP interface
Active low – initiates a write operation via the µP interface
µP interface data bus
µP interface address bus
Integrate and dump control logic output
Receive PN Generator Epoch signal (68 pin PLCC package only)
Receive PN generator output
Clock recovery input for narrow band mode, track-on (active high) output for spread spectrum mode – indicates
to external circuitry that the PN code is locked and tracking the received PN code
Pin for manufacturing test only – should be tied to ground for normal operation
Receive data input “Q” or QAM mode output clock to external shift register
Receive data input “I”
Reference voltage for integrate and dump comparators and switches
Receive VCO control voltage output
Receive DAC output during TRACK operation – Note: DACOUT0 and DACOUT1 are provided in the event that
separate gain control is necessary for SLIP and TRACK operation
Receive PLL DAC output during SLIP operation
Current reference for DACs and analog buffers – nominal resistor value of 20kΩ to AGND3
Reference voltage for ADC and DACs – value is mid-scale between VDD and GND
Analog input to the ADC – received signal strength indicator from the RF receiver, range is zero to VREF (full
scale on the internal ADC)
Analog input to the ADC – received signal strength indicator from the RF receiver, range is zero to VREF (full
scale on the internal ADC) This input is not usable in “SLIP” mode.
Transmit VCO voltage control output
AMI Semiconductor
– Sept. 06
www.amis.com
5
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