INTEGRATED CIRCUITS
DATA SHEET
SAA6750H
Encoder for MPEG2 image
recording (EMPIRE)
Product specification
Supersedes data of 2000 May 03
File under Integrated Circuits, IC02
2002 Jan 08
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
CONTENTS
1
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
3
4
5
6
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.6.3
7.7
7.7.1
FEATURES
GENERAL DESCRIPTION
General
Function
Application fields
General
Video editing (PC applications)
Camera signal transmission
Video recording for surveillance
Digital VCR
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Global architecture description
General
Architecture structure
Start-up and operating modes
Start-up requirements
Reset processing
Description of operating modes
Pin behaviour
Video front-end and formatter
General
Data input format
Functional description
Macroblock processor
General
Functional description
Bitstream assembly
General
Pre-packer and packer
Data output port
General
Data output format
Functional description
Application Specific Instruction-set Processor
(ASIP)
General
7.8
7.8.1
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.10
7.10.1
7.10.2
7.10.3
7.11
7.12
7.13
7.14
7.14.1
7.14.2
7.14.3
8
9
10
11
12
13
13.1
13.2
13.3
13.4
13.5
14
15
16
17
SAA6750H
Global controller
General
I
2
C-bus interface and controller
General
Special considerations
I
2
C-bus data transfer modes
I
2
C-bus memories and registers
I
2
C-bus initialization
DRAM interface
General
Application hints
Functional description
FIFO memories
Clock distribution
Input/output levels
Boundary scan test
General
Initialization of boundary scan circuit
Device identification codes
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I2C COMPONENTS
2002 Jan 08
2
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
1
FEATURES
SAA6750H
•
Digital YUV input according to
“ITU-T 601”
and
“ITU-T 656”
•
NTSC and PAL (720 pixels
×
480 lines at 60 Hz and
720 pixels
×
576 lines at 50 Hz)
•
Integrated colour conversion 4 : 2 : 2 to 4 : 2 : 0
•
Integrated format conversion to SIF format (optional)
•
Real time MPEG2 Simple Profile at Main Level
(SP@ML) encoding
•
IP frame or I frame only encoding supported
•
Programmable Group Of Pictures (GOP) size
•
Integrated motion estimation, half pixel accuracy
•
Motion compensated noise reduction
•
Elementary stream data output compliant to MPEG2
standard (“ISO
13818-2”)
•
Bitstream output compatible to 16-bit parallel interface
with Motorola (68xxx like) protocol style
•
No external host processor required
•
4
×
4 Mbit external DRAM required
•
I
2
C-bus controlled
•
Single external video clock 27 MHz
•
Power supply voltage 3.3 V
•
Digital inputs 5 V tolerant
•
Boundary Scan Test (BST) supported.
2
2.1
GENERAL DESCRIPTION
General
•
The patented, motion-compensated temporal noise
filtering which was developed by Philips for professional
equipment reduces noise in the input video before
compression is performed. This technique gives visible
improvements in picture quality, especially in the field of
home recordings with noisy signal sources where this
has proved to be of significant benefit.
Internally the SAA6750H uses a hardware solution for data
compression and a specially developed high performance
processor for control purposes.
2.2
Function
The SAA6750H is a stand-alone single chip video encoder
performing real time MPEG2 compression of digital video
data.
The video data input of the SAA6750H accepts a digital
YUV video data stream in ITU-T 601 format. PAL standard
at 50 Hz and 720 pixels by 576 lines, as well as NTSC at
60 Hz and 720 pixels by 480 lines, are covered. The video
synchronization may either follow ITU-T 656
recommendation or can also be supplied by external
signals. The external reference clock of 27 MHz to
pin VCLK has to be synchronized to the video data. The
product family SAA7111 of Philips Semiconductors
provides a suitable video data stream and reference clock.
Other sources are also supported by the flexible I
2
C-bus
controlled data input interface of the SAA6750H.
See Section 7.3 for detailed information.
An internal 4 : 2 : 2 to 4 : 2 : 0 colour format conversion is
performed. Optionally, a ITU-T 601 to SIF format
conversion may be activated by the I
2
C-bus control
settings.
The real time data encoding part of the SAA6750H
combines high-compression rates with high quality picture
performance. This is achieved by the integration of Philips
unique motion estimation algorithm and a patented
motion-compensated noise filtering. The compression
algorithm uses I or IP mode encoding. Normally it selects
automatically the suitable mode but may also be forced to
I mode operating only by the I
2
C-bus control settings.
The SAA6750H is a new approach towards a stand-alone
MPEG2 video encoder IC. It combines high quality
SP@ML compliant real time encoding with
cost-effectiveness, allowing for the first time the use of an
MPEG2 encoder IC in applications and markets with a
high cost pressure. This has been achieved by means of a
number of innovations in architecture and algorithms
developed by the Philips Research Laboratories, e.g.:
•
The unique motion estimation algorithm supports highly
efficient encoding by using only I frame and IP frame
mode. B frames need not be used. This leads to a
significantly smaller internal circuitry and also reduces
DRAM memory requirements from at least 4 to 2 Mbyte.
In addition, the absence of B frames simplifies editing of
the compressed data stream.
2002 Jan 08
3
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
In contrast to the encoding part which is designed in
dedicated hardware, control functions and data stream
handling tasks such as e.g. header generation and bit-rate
control are carried out by a dedicated control processor,
the so-called Application Specific Instruction-set
Processor (ASIP). The ASIP’s microcode is contained in
an internal RAM and is loaded via the I
2
C-bus before start
of operation.
The ASIP is able to communicate with the outside world
via the I
2
C-bus.
The SAA6750H generates an MPEG2 Elementary
Stream (ES) in accordance with the MPEG2 standard
(“ISO
13818-2”).
The 16-bit data output interface supports
Motorola (68xxx like) protocol style.
Data processing and control functions are managed by
loosely coupled processes. FIFO memories are used to
connect these processes. In addition to these internal
storages the SAA6750H needs 4
×
4 Mbit of external
DRAM memory (t
RAC
= 60 ns). A block diagram is shown
in Fig.1.
Selectable I
2
C-bus addresses and a special reset mode
affecting the output pin behaviour allow the use of two
SAA6750H devices in one application.
2.3
2.3.1
Application fields
G
ENERAL
2.3.2
SAA6750H
V
IDEO EDITING
(PC
APPLICATIONS
)
For video editing the SAA6750H can be interfaced
gluelessly to a video input processor with ITU-T 656
compliant digital video output. In order to link the
SAA6750H to the PC, the use of the PCI bridge SAA7146
is recommended. By this bridge the MPEG2 video ES can
be transmitted via the PCI-bus to a HardDisc (HD).
Furthermore all the I
2
C-bus settings can be send from
the PC via the bridge to the I
2
C-bus components on the
encoder board. The SAA7146 supports Pulse Code
Modulation (PCM) audio capturing. Multiplexing with an
audio stream or audio encoding can be done by the CPU
of the PC. A block diagram is shown in Fig.18.
2.3.3
C
AMERA SIGNAL TRANSMISSION
In this application the SAA6750H will be located inside a
camera to compress the received digital video data for
transmission.
2.3.4
V
IDEO RECORDING FOR SURVEILLANCE
For surveillance systems VCRs with a huge amount of
storage capacity are required. A high picture resolution is
very important when there is action in the captured picture.
The SAA6750H can control the encoded bit-rate by motion
detection by its integrated motion estimation algorithm.
Doing so the bit-rate can vary from 0.5 to 10 Mbit/s.
VCRs with a storage space of 6 month are possible.
2.3.5
D
IGITAL
VCR
The SAA6750H can be applied within the following
application domains:
•
Video editing (PC applications)
•
Camera signal transmission
•
Digital Versatile Disc (DVD) recording
•
Video recording for surveillance
•
Digital VCR.
All those systems have to compress video data in order to
manage the storage or transmission of digitized video
data. The SAA6750H can be handled for most of the
applications as a stand-alone device. That means at
start-up a microcode and a couple of the I
2
C-bus settings
are loaded and the SAA6750H is started. If needed,
settings such as GOP size or bit-rate are changed
on-the-fly via the I
2
C-bus.
In stand-alone VCRs the SAA6750H works together with
an audio encoder and a multiplexer. The SAA6750H is
clocked by the video clock of the video input processor
(SAA7111 or derivatives). A master clock is derived from
the frame pulse. The video clock and master clock domain
are de-coupled by a FIFO. The audio clock can be derived
from the master clock. The video Packetized Elementary
Stream (PES) packetizer has to take care of the fullness of
the output buffer of the SAA6750H.
2002 Jan 08
4
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
3
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD(tot)
P
tot
f
VCLK
f
SCL
B
V
IH
V
IL
V
OH
V
OL
T
amb
4
digital supply voltage
total digital supply current
total power dissipation
video clock frequency
I
2
C-bus clock frequency
output bit-rate
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
ambient temperature
PARAMETER
MIN.
3.0
−
−
25.6
100
1.5
2.0
−0.5
2.4
−
0
SAA6750H
TYP.
3.3
0.22
0.73
27.0
−
−
−
−
−
−
−
MAX.
3.6
0.56
2.0
28.6
400
40
5.5
+0.8
V
DD
0.4
70
UNIT
V
A
W
MHz
kHz
Mbit/s
V
V
V
V
°C
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
SQFP208
DESCRIPTION
plastic shrink quad flat package; 208 leads (lead length 1.3 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT316-1
SAA6750H
2002 Jan 08
5
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