INTEGRATED CIRCUITS
DATA SHEET
SAA7151B
Digital multistandard colour
decoder with SCART interface
(DMSD2-SCART)
Product specification
File under Integrated Circuits, IC02
April 1993
Philips Semiconductors
Product specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
FEATURES
•
8-bit performance on chip for luminance and
chrominance signal processing for PAL, NTSC and
SECAM standards
•
Separate 8-bit luminance and 8-bit chrominance input
signals from Y/C, CVBS, S-Video (S-VHS or Hi8)
sources
•
SCART signal insertion by means of RGB/YUV
convertion; fast switch handling
•
Horizontal and vertical sync detection for all standards
•
Real time control output RTCO
•
Fast sync recovery of vertical blanking for VCR signals
(bottom flutter compensation)
•
Controls via the I
2
C-bus
•
User programmable aperture correction (horizontal
peaking)
•
Cross-colour reduction by chrominance comb-filtering
(NTSC) or by special cross-colour cancellation
(SECAM)
•
8-bit quantization of output signals in 4:1:1 or 4:2:2
formats
•
720 active samples per line
SAA7151B
•
The YUV bus supports a data rate of 13.5 MHz
(CCIR 601).
– (864
×
f
H
) for 50 Hz
– (858
×
f
H
) for 60 Hz
•
Compatible with memory-based features (line-locked
clock)
•
One 24.576 MHz crystal oscillator for all standards
GENERAL DESCRIPTION
The SAA7151B is a digital multistandard colour-decoder
having two 8-bit input channels, one for CVBS or Y, the
other for chrominance or time-multiplexed
colour-difference signals.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
V
I
V
O
T
amb
PARAMETER
supply voltage (pins 5, 18, 28, 37 and 52)
total supply current (pins 5, 18, 28, 37 and 52)
input levels
output levels
operating ambient temperature
0
−
−
MIN.
4.5
5
100
TYP.
MAX.
5.5
250
TTL-compatible
TTL-compatible
70
°C
V
mA
UNIT
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA7151B
Note
1. SOT188-2; 1996 December 16.
PACKAGE
PINS
68
PIN POSITION
mini-pack PLCC
MATERIAL
plastic
CODE
SOT188
(1)
April 1993
2
ull pagewidth
April 1993
MUXC
CPI
SYIS
GPSW2
test pins
SCART
FSI FSO
VSS1 to VSS4
19, 38, 51, 67
COMPONENT PROCESSING;
SCART INTERFACE CONTROL;
FAST SWITCH INSERTION
68
44
65
32
24
25
1, 2
66
GPSW1
+5
V
VDD1 to VDD4
BLOCK DIAGRAM
Philips Semiconductors
5, 18, 28, 52
RESN
3
POWER-ON
RESET
SAA7151A
45 to 50,
53, 54
CHROMINANCE PROCESSOR
55 to 62
OUTPUT
INTERFACE
42
64
LUMINANCE
PROCESSOR
clock
status
37
+5
V
36
35
33
SYNCHRONIZATION
CLOCK
34
VDDA
LFCO
VSSA
XTAL
XTALI
39
4
27
Y output
(Y7 to Y0)
UV output
(UV7 to UV0)
HREF
FEIN
CVBS0 to
CVBS7
14 to 17
20 to 23
INPUT
INTERFACE
CUV0 to
CUV7
6 to 13
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
3
63
26
29
30
31
HCL HSY
VS
HS
ODD
CREF
STATUS
REGISTER
SDA
40
SCL
41
I
2
C-BUS
CONTROL
43
IICSA
LL27
MEH292
GPSW0
Product specification
SAA7151B
Fig.1 Block diagram (application circuits see Figs 17, 18 and 19).
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
PINNING
SYMBOL
SP
AP
RESN
CREF
V
DD1
CUV0
CUV1
CUV2
CUV3
CUV4
CUV5
CUV6
CUV7
CVBS0
CVBS1
CVBS2
CVBS3
V
DD2
V
SS1
CVBS4
CVBS5
CVBS6
CVBS7
GPSW1
GPSW2
HCL
LL27
V
DD3
HSY
VS
HS
RTCO
XTAL
XTALI
V
SSA
LFCO
V
DDA
V
SS2
April 1993
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
+5
V supply input 2
ground 1 (0 V)
DESCRIPTION
connected to ground (shift pin for testing)
connected to ground (action pin for testing)
reset, active-LOW
SAA7151B
clock reference, sync from external to ensure in-phase signals on the Y-, CUV- and YUV-bus
+5
V supply input 1
chrominance input data bits CUV7 to CUV0 (digitized chrominance signals in two’s complement
format from a S-Video source (S-VHS, Hi8) or time-multiplexed colour-difference signals from a
YUV(RGB) source or both in combination)
CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two’s complement format)
CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two’s complement format)
status bit output FSST0 or port 1 output for general purpose (programmable by subaddress 0C)
status bit output FSST1 or port 2 output for general purpose (programmable by subaddress 0C)
black level clamp pulse output (begin and stop programmable), e.g. for TDA8708A (ADC)
line-locked system clock input signal (27 MHz)
+5
V supply input 3
hor. sync pulse reference output (begin and stop programmable), e.g. for gain adj.TDA8708A
(ADC)
vertical sync output signal (Fig.11)
horizontal sync output signal (Fig.16; start point programmable)
real time control output; serial increments of HPLL and FSCPLL and status PAL or SECAM
sequence (Fig.10)
24.576 MHz clock output (open-circuit for use with external oscillator)
24.576 MHz connection for crystal or external oscillator (TTL compatible squarewave)
analog ground
line frequency control output signal, multiple of horizontal frequency (nominal 6.75 MHz)
+5
V supply input for analog part
ground 2 (0 V)
4
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SYMBOL
ODD
SDA
SCL
HREF
IICSA
CPI
Y7
Y6
Y5
Y4
Y3
Y2
V
SS3
V
DD4
Y1
Y0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
GPSW0
FEIN
MUXC
FSO
V
SS4
FSI
PIN
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
port output for general purpose (programmable by subaddress 0D)
UV signal output bits UV7 to UV0, part of the digital YUV-bus
ground 3 (0 V)
+5
V supply input 4
Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus
Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus
DESCRIPTION
odd/even field identification output (odd = HIGH)
I
2
C-bus data line
I
2
C-bus clock line
horizontal reference for YUV data outputs (for active line 720Y samples long)
set module address input of I
2
C-bus (LOW = 1000 101X; HIGH = 1000 111X)
clamping pulse input (digital clamping of external UV signals)
SAA7151B
fast enable input (active-LOW to control fast switching due to YUV data; HIGH = YUV high-Z
multiplexer control output; source select signal for external ADC (UV signal multiplexing)
fast switch and sync insertion output; gated FS signal from FSI or sync insertion pulse in full screen
RGB mode
ground 4 (0 V)
fast switch input signal fed from SCART/peri-TV connector (indicates fast insertion of RGB signals)
April 1993
5
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