Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
FEATURES
•
Monolithic CMOS 3.3 V (5 V) device
•
Digital PAL/NTSC encoder
•
System pixel frequency 13.5 MHz
•
Accepts MPEG decoded data on 8-bit wide input port;
input data format Cb-Y-Cr (CCIR 656), SAV and EAV
•
Three DACs for Y, C and CVBS, two times oversampled
with 10 bit resolution
•
Real time control of subcarrier
•
Cross colour reduction filter
•
Closed captioning encoding and WST- and
NABTS-Teletext encoding including sequencer and filter
•
Line 23 wide screen signalling encoding
•
Fast I
2
C-bus control port (400 kHz)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal colour bar generator (CBG)
•
2
×
2 bytes in lines 20 (NTSC) for copy guard
management system can be loaded via I
2
C-bus
•
Down-mode of DACs
•
Controlled rise/fall times of synchronization and
blanking output signals
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
ILE
DLE
T
amb
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y, C, and CVBS without load
(peak-to-peak value)
load resistance
LF integral linearity error
LF differential linearity error
operating ambient temperature
1.2
75
−
−
0
PARAMETER
SAA7120; SAA7121
•
Macrovision Pay-per-View copy protection system rev.7
and rev.6.1 as option.
This applies to SAA7120 only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductors
sales office for more information.
•
QFP44 package.
GENERAL DESCRIPTION
The SAA7120; SAA7121 encodes digital YUV video data
to an NTSC or PAL CVBS or S-Video signal.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip DACs.
MIN.
3.1
3.0
−
−
TYP.
3.3
3.3
−
−
1.35
−
−
−
−
MAX.
3.5
3.6
62
38
1.45
300
±3
±1
+70
UNIT
V
V
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
1997 Jan 06
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
PINNING
SYMBOL
res.
SP
AP
LLC
V
SSD1
V
DDD1
RCV1
RCV2
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
DDD2
V
SSD2
RTCI
res.
SA
res.
res.
C
V
DDA1
res.
Y
V
DDA2
res.
CVBS
V
DDA3
V
SSA1
V
SSA2
XTALO
XTALI
V
DDA4
XCLK
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I/O
−
I
I
I
I
I
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
−
I
−
−
O
I
−
O
I
−
O
I
I
I
O
I
I
O
digital supply voltage 2
digital ground 2
reserved
DESCRIPTION
SAA7120; SAA7121
test pin; connected to digital ground for normal operation
test pin; connected to digital ground for normal operation
line-locked clock; this is the 27 MHz master clock for the encoder
digital ground 1
digital supply voltage 1
raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse
MPEG port; it is an input for
“CCIR 656”
style multiplexed Cb Y, Cr data
Real Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to pin RTCO of the decoder to improve the signal quality
reserved
the I
2
C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH
reserved
reserved
analog output of the chrominance signal
analog supply voltage 1 for the C DAC
reserved
analog output of VBS signal
analog supply voltage 2 for the Y DAC
reserved
analog output of the CVBS signal
analog supply voltage 3 for the CVBS DAC
analog ground 1 for the DACs
analog ground 2 for the oscillator and reference voltage
crystal oscillator output (to crystal)
crystal oscillator input (from crystal); if the oscillator is not used, this pin should be
connected to ground
analog supply voltage 4 for the oscillator and reference voltage
clock output of the crystal oscillator
1997 Jan 06
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
SYMBOL
V
SSD3
V
DDD3
RESET
SCL
SDA
TTXRQ
TTX
PIN
38
39
40
41
42
43
44
I/O
I
I
I
I
I/O
O
I
digital ground 3
digital supply voltage 3
DESCRIPTION
reset input, active LOW; after reset is applied, all digital I/Os are in input mode;
the I
2
C-bus receiver waits for the START condition
I
2
C-bus serial clock input
I
2
C-bus serial data input/output
teletext request output, indicating when bit stream is valid
teletext bit stream input
39 VDDD3
43 TTXRQ
40 RESET
36 VDDA4
38 VSSD3
35 XTALI
37 XCLK
handbook, full pagewidth
34 XTALO
42 SDA
41 SCL
44 TTX
res. 1
SP 2
AP 3
LLC 4
VSSD1 5
VDDD1 6
RCV1 7
RCV2 8
MP7 9
MP6 10
MP5 11
33 VSSA2
32 VSSA1
31 VDDA3
30 CVBS
29 res.
SAA7120
SAA7121
28 VDDA2
27 Y
26 res.
25 VDDA1
24 C
23 res.
MP4 12
MP3 13
MP2 14
MP1 15
MP0 16
VDDD2 17
VSSD2 18
RTCI 19
res. 20
SA 21
res. 22
MBH790
Fig.2 Pin configuration.
1997 Jan 06
5
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