INTEGRATED CIRCUITS
DATA SHEET
SAA7715AH
Digital Signal Processor
Preliminary specification
2003 Mar 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor
CONTENTS
1
1.1
1.2
2
3
4
5
6
7
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
8.5
8.5.1
8.5.2
8.6
8.7
8.8
8.9
8.10
FEATURES
Hardware
Possible firmware
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
PLL clock division factors for different clock
inputs
The word select PLL
The Filter Stream DAC (FSDAC)
Interpolation filter
Noise shaper
Function of pin POM
Power off plop suppression
Pin VREFDA for internal reference
Supply of the analog outputs
External control pins
Digital serial inputs/outputs and SPDIF inputs
Digital serial inputs/outputs
SPDIF inputs
I
2
C-bus interface (pins SCL and SDA)
Reset
Power-down mode
Power supply connection and EMC
Test mode connections (pins TSCAN, RTCB
and SHTCB)
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
18.5
19
20
21
22
I
2
C-BUS PROTOCOL
SAA7715AH
Addressing
Slave address (pin A0)
Write cycles
Read cycles
Program RAM
Data word alignment
I
2
C-bus memory map specification
I
2
C-bus memory map definition
Table definitions
SOFTWARE IN ROM DESCRIPTION
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
I
2
S-BUS TIMING
I
2
C-BUS TIMING
APPLICATION DIAGRAM
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2003 Mar 13
2
Philips Semiconductors
Preliminary specification
Digital Signal Processor
1
1.1
FEATURES
Hardware
SAA7715AH
•
24-bit Philips 70 MIPS DSP core (24-bit data path and
12/24-bit coefficient path)
•
1.5 kbyte of downloadable DSP program memory
(PRAM)
•
2 kbyte of DSP program memory (PROM)
•
2.875 kbyte of re-programmable DSP data memory
(XRAM)
•
1.5 kbyte of re-programmable DSP coefficient memory
(YRAM)
•
Four stereo digital serial inputs (8 channels) with
common BCK and WS. To these inputs the I
2
S-bus
format or LSB-justified formats can be applied
•
One stereo bitstream DAC (2 channels) with 64 fold
oversampling and noise shaping
•
Selectable clock output (pin SYSCLK) for external slave
devices (128f
s
to 512f
s
)
•
Four stereo digital serial outputs (8 channels) with
selectable I
2
S-bus or LSB-justified format
•
Two SPDIF inputs combined with digital serial input
•
On-board WS_PLL generates clock for on-board DAC
and output pin SYSCLK
•
I
2
C-bus controlled (including fast mode)
•
Programmable Phase-Locked Loop (PLL) derives the
clock for the DSP from the CLK_IN input
• −40
to +85
°C
operating temperature range
•
Supply voltage only 3.3 V
•
All digital inputs are tolerant for 5 V input levels
•
Power-down mode for low current consumption in
standby mode
•
Optimized pinning for applications with other Philips
DACs (such as UDA1334, UDA1355 and UDA1328).
1.2
Possible firmware
•
Incredible surround
•
Incredible mono (Imono)
•
DPL virtualizer
•
Dolby digital virtualizer (DVD post-processing)
•
Dynamic compressor
•
Spectral enhancer
•
Equalizer with peaking/shelving filters
•
DC filters
•
Bass/treble control
•
Dynamic loudness
•
Tone/noise generator
•
Graphical spectrum analyser
•
Configurable Delay Unit (DLU)
•
Sound steering/elevation for car applications
•
Sample Rate Conversion (SRC).
2
APPLICATIONS
•
As co-processor for a car radio DSP in a car radio
application for additional acoustic enhancements
(sound steering/sound elevation/signal processing)
•
Multichannel audio: in DVD and Home theatre
applications as post-processing device such as signal
virtualization (virtual 3D surround) and acoustic
enhancement, tone control, volume control and
equalizers
•
Multichannel decoding: Dolby Pro Logic and virtual
3D surround
•
PC/USB audio applications: stereo widening (Incredible
surround), sound steering, sound positioning and
speaker equalization.
•
Dolby®
(1)
Pro Logic decoding
•
Smoothed volume control (without zipper noise)
•
Automatic Volume Levelling (AVL)
•
Dynamic bass enhancement
•
Ultra bass
(1)
Dolby
— Available only to licensees of Dolby Laboratories
Licensing Corporation, San Francisco, CA94111, USA, from
whom licensing and application information must be obtained.
Dolby is a registered trade-mark of Dolby Laboratories
Licensing Corporation.
2003 Mar 13
3
Philips Semiconductors
Preliminary specification
Digital Signal Processor
3
GENERAL DESCRIPTION
SAA7715AH
The SAA7715AH can be configured for various audio
applications by downloading the dedicated DSP program
code into the DSP program RAM or using the ROM or a
combination of both. During the Power-down mode the
contents of the memories and all other settings will keep
their values. The SAA7715AH can be initialized using the
I
2
C-bus interface.
Several system application examples, based on this
existing SAA7715AH, are available for a wide range of
audio applications (e.g car radio DSP,
DVD post-processing, Dolby Pro Logic, PC/USB audio
and more) which can be used as a reference design for
customers.
The SAA7715AH is a cost effective and powerful high
performance 24-bit programmable DSP for a variety of
digital audio applications. This DSP device integrates a
24-bit DSP core with programmable memories (program
RAM/ROM, data and coefficient RAM), 4 digital serial
inputs, 4 digital serial outputs, 2 separate SPDIF
receivers, a stereo FSDAC, a standard Philips I
2
C-bus
interface, a phase-locked loop for the DSP clock
generation and a second phase-locked loop for system
clock generation (internal and external DAC clocks).
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
operating supply voltage
supply current of the digital
part
supply current of the analog
part
total power dissipation
CONDITIONS
MIN.
TYP.
3.3
95
20
380
400
44.1
−85
−37
100
−
−
MAX.
3.45
−
−
−
−
96
−
−
−
24.576
70
UNIT
V
mA
mA
mW
µA
kHz
dB(A)
dB(A)
dB(A)
MHz
MHz
MHz
V
DD
I
DDD
I
DDA
P
tot
I
POWERDOWN
f
s
(THD + N)/S
DAC
all pins V
DD
with respect to 3.15
pins V
SS
high activity of the DSP at
DSPFREQ frequency
zero input and output
signal
high activity of the DSP at
DSPFREQ frequency
−
−
−
−
32
−
−
−
8.192
16.384
−
DC supply current of the total pin POWERDOWN
chip in Power-down mode
enabled
sample frequency
total harmonic
distortion-plus-noise to
signal ratio of DAC
signal-to-noise ratio of DAC
clock input frequency
maximum DSP clock
frequency
at IIS_WS1, SPDIF1 or
SPDIF2 input
at 0 dB
at
−60
dB
code = 0
DIV_CLK_IN = LOW
DIV_CLK_IN = HIGH
S/N
DAC
f
CLK_IN
DSPFREQ
11.2896 12.288
5
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7715AH
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
VERSION
SOT307-2
2003 Mar 13
4
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2003 Mar 13
RESERVED1
RESERVED2
handbook, full pagewidth
6
Philips Semiconductors
Digital Signal Processor
BLOCK DIAGRAM
RESERVED3
SPDIF2
SPDIF1
VDDA1
VDDA2
VSSA1
VSSA2
VDDI1
24
1
2
3
5
25
4
7
8
VSSI1
14
VDDE
VSSE
35
17
23
16
37
15
21
VSSI2
10
31
30
IIS_BCK1
IIS_WS1
IIS_IN1
IIS_IN4
IIS_OUT1
IIS_OUT2
IIS_OUT3
IIS_OUT4
IIS_BCK
IIS_WS
XRAM
YRAM
29
28
33
SAA7715AH
IIS_IN2
6
32
DSP CORE
CLK_IN
DIV_CLK_IN
POWERDOWN
DSP_INOUT7
DSP_INOUT6
DSP_INOUT5
SHTCB
TSCAN
RTCB
A0
SYSCLK
DSP_RESET
SDA
SCL
5
34
36
IIS_IN3
9
VOUTL
VOUTR
POM
VREFDA
÷
2
S
PRAM
PLL
DSP CLOCK
PROM
STEREO
DAC
n
×
fs
CLOCK
39
38
TCB
I
2
C-BUS
WS_PLL
22
41
44
43
42
40
20
19
26
13
12
11
27
18
MHC320
Preliminary specification
SAA7715AH
Fig.1 Block diagram.
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