MK1493-01
PCI Clock Generator
Description
The MK1493-01 is a general purpose clock generator
part that provides an integrated clocking solution for
PCI /networking applications. It provides 8 individually
programmable PCI clocks, 2 CPU clocks, additional
fixed PCI clocks and a 25 MHz reference clock for LAN
support. This part incorporates ICS’s newest clock
technology, offering more robust features and
functionality. Using a serially programmable SMBus
interface, the MK1493-01 can select the output clock
frequency, and enabling/disabling each individual
output clock.
Features
•
8 PCI clocks at 25, 33, 50, 66.66 MHz individually pin
selectableand serioal port slectable
•
•
•
•
•
•
•
•
•
•
•
2 CPU clocks at 100 MHz
2 PCI clocks at 66.66 MHz
1 PCI clock @ 50 MHz
25 MHz reference clock
SMBus
Programming
Power-up default frequency can be selected through
FS inputs
25 MHz crystal or clock input required
PCICLK cycle to cycle jitter <250ps
CPUCLK cycle to cycle jitter <100ps
Packaged in 48-pin (240mil) TSSOP Package
Operating Voltage 3.3V + - 5%
Block Diagram
VDD
7
8
SCLK
SDATA
FS(0:7)_A
FS(0:7)_B
8
8
PLL
Divider
Buffer Circuits
SMBus Programmable
2
PCICLK(0:7)
Each PCI Output
Clock Individually
Programmable
CPUCLK(100MHz)
2
66M CLK
50M CLK
X1/CLK
25 MHz
X2
7
GND
Clock Buffer/
Crystal
Ocsillator
REFCLK
MDS 1493-01 B
1
Revision 021204
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1493-01
PCI Clock Generator
Pin Assignment
FS3_A
FS2_A
FS1_A
FS0_A
GND
VDD
SCL
SDA
GND
X1
X2
VDD
REF25
VDD
GND
GND
VDD
CPUCLK0
CPUCLK1
FS7_B
CLK50
FS6_B
FS5_B
FS4_B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FS4_A
FS5_A
FS6_A
FS7_A
FS0_B
FS1_B
PCICLK7
GND
VDD
PCICLK6
PCICLK5
PCICLK4
FS2_B
VDD
GND
CLK66A0
CLK66A1
FS3_B
VDD
GND
PCICLK2
PCICLK1
PCICLK0
PCICLK3
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
Pin
Name
FS3_A
FS2_A
FS1_A
FS0_A
GND
VDD
SCL
SDA
GND
X1/ICLK
X2
VDD
Pin
Type
Input
Input
Input
Input
Power
Power
Input
Input
Power
Input
XO
Power
Pin Description
Frequency select input pin for PCI CLK3 per per table 1
.
Pull up resistor.
Frequency select input pin for PCI CLK2 per per table 1
.
Pull up resistor.
Frequency select input pin for PCI CLK1 per per table 1
.
Pull up resistor.
Frequency select input pin for PCI CLK0 per per table 1
.
Pull up resistor.
Connect to ground.
Connect to +3.3 V.
Clock pin for SMBus circuitry, 5 V tolerant.
Data pin for SMBus circuitry, 5 V tolerant.
Connect to ground.
Crystal connection/input clock. Connect to a 25 MHz fundamental mode crystal.
Crystal connection. Connect to a 25 MHz fundamental mode crystal or leave open.
Connect to +3.3 V.
MDS 1493-01 B
2
Revision 021204
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1493-01
PCI Clock Generator
Pin
Number
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin
Name
REF25
VDD
GND
GND
VDD
CPUCLK0
CPUCLK1
FS7_B
CLK50
FS6_B
FS5_B
FS4_B
PCICLK3
PCICLK0
PCICLK1
PCICLK2
GND
VDD
FS3_B
CLK66A1
CLK66A0
GND
VDD
FS2_B
PCICLK4
PCICLK5
PCICLK6
VDD
GND
PCICLK7
FS1_B
FS0_B
FS7_A
FS6_A
FS5_A
FS4_A
Pin
Type
Pin Description
Output Buffered reference output of 25 MHz crystal input.
Power
Power
Power
Power
Connect to +3.3 V.
Connect to ground.
Connect to ground.
Connect to +3.3 V.
Output 100 MHz CPU clock.
Output 100 MHz CPU clock.
Input
1 of 4 frequency select input pin for PCI CLK7 per per table 1
.
Pull-up resistor.
Output 50 MHz clock output.
Input
Input
Input
Frequency select input pin for PCI CLK6 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK5 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK4 per per table 1
.
Pull-up resistor.
Output PCI CLK3.
Output PCI CLK0.
Output PCI CLK1.
Output PCI CLK2.
Power
Power
Input
Connect to ground.
Connect to +3.3 V.
Frequency select input pin for PCI CLK3 per per table 1
.
Pull-up resistor.
Output Additional PCI Clock (fixed frequency 66 MHz ).
Output Additional PCI Clock (fixed frequency 66 MHz ).
Power
Power
Input
Connect to ground.
Connect to +3.3 V.
Frequency select input pin for PCI CLK2 per per table 1
.
Pull-up resistor.
Output PCI CLK4.
Output PCI CLK5.
Output PCI CLK6.
Power
Power
Connect to +3.3 V.
Connect to ground.
Output PCI CLK7.
Input
Input
Input
Input
Input
Input
Frequency select input pin for PCI CLK1 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK0 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK7 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK6 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK5 per per table 1
.
Pull-up resistor.
Frequency select input pin for PCI CLK4 per per table 1
.
Pull-up resistor.
MDS 1493-01 B
3
Revision 021204
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1493-01
PCI Clock Generator
Table 1. Frequency Select
FS(0:7)_B
0
0
1
1
FS(0:7)_A
0
1
0
1
PCICLK(0:7)
25 MHz
33.33 MHz
50 MHz
66.66 MHz
Power Groups
Pin Number
VDD
12
30, 40
35
6
17
14
GND
9
29, 41
34
5
16
15
Ref, Crystal Osc Power
supply
PCICLK
PCI 66 clocks
SCLK
CPU Clocks(100MHz)
PLL
Beginning Byte N
ACK
O
O
O
Byte N + X - 1
ACK
P
stoP bit
Data Byte Count = X
ACK
Description
Index Block Write Operation
Controller (Host)
T
WR
starT bit
WRite
ACK
Beginning Byte = N
ACK
Slave Address D2
(H)
ICS (Slave/Receiver)
General I C Serial Interface
Information
How to Write:
2
X Byte
O
O
O
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the beginning byte location =
N
ICS clock will
acknowldege
Controller (host) starts sending Byte
N through Byte
N+X-1(note 2)
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
MDS 1493-01 B
4
Revision 021204
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1493-01
PCI Clock Generator
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the beginning byte
location = N
ICS clock will
acknowldege
Controller (host) will send a separate start bit
Controller (host) sends the read address D3
(H)
ICS clock will
acknowldege
ICS clock will send the data byte count = X
ICS clock sends Byte
N+X-1
ICS clock sends
Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T
WR
starT bit
WRite
ACK
Beginning Byte = N
ACK
RT
RD
Repeat starT
ReaD
ACK
Data Byte Count=X
ACK
Beginning Byte N
ACK
X Byte
O
O
O
Byte N + X - 1
N
P
Not
stoP bit
O
O
O
Slave Address D3
(H)
Slave Address D2
(H)
ICS (Slave/Receiver)
SMBus Table 2: Read-Back Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Frequency
Selection
See Frequency table 3
FS vs. SMBus
prog
Name
Control
Function
RESERVED
HW/SW select
RESERVED
RESERVED
RESERVED
RW
HW
SW
Type
0
1
PWD
0
0
0
0
0
0
0
0
MDS 1493-01 B
5
Revision 021204
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
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