notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
1
IS41C44002C
IS41LV44002C
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CAS
WE
OE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
I/O0-I/O3
MEMORY ARRAY
4,194,304 x 4
A0-A10
ADDRESS
BUFFERS
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
EDO Page-Mode Read
1st Cycle:
2nd Cycle:
EDO Page-Mode Write
1st Cycle:
2nd Cycle:
EDO Page-Mode
1st Cycle:
Read-Write
2nd Cycle:
Hidden Refresh
Read
Write
(1)
RAS-Only Refresh
CBR Refresh
Note:
1. EARLY WRITE only.
RAS
H
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
WE
X
H
L
H→L
H
H
L
L
H→L
H→L
H
L
X
X
OE
X
L
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
D
out
D
in
D
out
, D
in
D
out
D
out
D
in
D
in
D
out
, D
in
D
out
, D
in
D
out
D
out
High-Z
High-Z
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
IS41C44002C
IS41LV44002C
Functional Description
The IS41C/41LV44002C is a CMOS DRAMs optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 11 address bits. These are entered 11 bits
(A0-A10) at a time for the 2K refresh device. The row ad-
dress is latched by the Row Address Strobe (RAS). The
column address is latched by the Column Address Strobe
(CAS).
RAS
is used to latch the first nine bits and
CAS
is used the latter ten bits.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in
each 32 ms period. There are two ways to refresh the
memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS LOW. In CAS-before-RAS
refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing
RAS LOW and
it is terminated by returning both
RAS
and
CAS HIGH.
To ensures proper device operation and data integrity
any memory cycle, once initiated, must not be ended or
aborted before the minimum t
ras
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
rp
, t
cp
has elapsed.
Power-On
After application of the V
dd
supply, an initial pause of 200
µs is required followed by a minimum of eight initializa-
tion cycles (any combination of cycles containing a RAS
signal).
During power-on, it is recommended that RAS track with
V
dd
or be held at a valid V
ih
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE HIGH. The
column address must be held for a minimum time speci-
fied by t
ar
. Data Out becomes valid only when t
rac
, t
aa
,
t
cac
and t
oea
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
08/09/2010
3
IS41C44002C
IS41LV44002C
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
t
V
dd
I
out
P
d
T
a
T
stg
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
–0.5 to +4.6
–1.0 to +7.0
–0.5 to +4.6
50
1
-40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
dd
V
ih
V
il
i
il
i
io
V
oh
V
ol
T
a
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Test Condition
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.0
2.0
–1.0
–0.3
–5
–5
2.4
2.4
—
—
0
-40
Typ.
5.0
3.3
—
—
—
—
Max. Unit
5.5
V
3.6
V
dd
+ 1.0 V
V
dd
+ 0.3
0.8
V
0.8
5
µA
5
—
—
0.4
0.4
+70
+85
µA
V
V
°C
Any input 0V ≤ V
in
≤
V
dd
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
out
≤
V
dd
i
oh
= –5.0 mA
i
oh
= –2.0 mA
i
ol
= 4.2 mA
i
ol
= 2 mA
5V
3.3V
5V
3.3V
—
—
Commercial Ambient Temperature
Industrial Ambient Temperature
CAPACITANCE
(1,2)
Symbol
C
in
1
C
in
2
C
io
Parameter
Input Capacitance: A0-A10
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a
= 25°C, f = 1 MHz.
4
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