H
Isolated 15-bit A/D Converter
Technical Data
HCPL-7860
HCPL-0870, -7870
Features
• 12-bit Linearity
• 700 ns Conversion Time
(Pre-Trigger Mode 2)
• 5 Conversion Modes for
Resolution/Speed Trade-Off;
12-bit Effective Resolution
with 18
µ
s Signal Delay
(14-bit with 94
µ
s)
• Fast 3
µ
s Over-Range
Detection
• Serial I/O (SPI
®
, QSPI
®
and
Microwire
®
Compatible)
•
±
200 mV Input Range with
Single 5 V Supply
• 1% Internal Reference
Voltage Matching
• Offset Calibration
• -40
°
C to +85
°
C Operating
Temperature Range
• 15 kV/
µ
s Isolation Transient
Immunity
• Regulatory Approvals; UL,
CSA, VDE
DIGITAL CURRENT SENSOR
+
ISOLATION
BOUNDARY
+
OUTPUT
DATA
INPUT
CURRENT
ISOLATED
MODULATOR
DIGITAL
INTERFACE IC
Hewlett-Packard’s Isolated A/D Converter delivers the reliability, small size, superior
isolation and over-temperature performance motor drive designers need to
accurately
measure current at half the price of traditional solutions.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
1-260
MICRO-CONTROLLER
HP7860
YYWW
HPx870
YYWW
5965-5255E
Digital Current Sensing
Circuit
As shown in Figure 1, using the
Isolated 2-chip A/D converter to
sense current can be as simple as
connecting a current-sensing
resistor, or shunt, to the input
and reading output data through
the 3-wire serial output interface.
By choosing the appropriate
shunt resistance, any range of
current can be monitored, from
less than 1 A to more than 100 A.
Even better performance can be
achieved by fully utilizing the
more advanced features of the
Isolated A/D converter, such as
the pre-trigger circuit which can
reduce conversion time to less
than 1
µs,
the fast over-range
detector for quickly detecting
short circuits, different conversion
modes giving various resolution/
speed trade-offs, offset calibra-
tion mode to eliminate initial
offset from measurements, and
an adjustable threshold detector
for detecting non-short circuit
overload conditions.
NON-ISOLATED
+5V
ISOLATED
+5V
+
INPUT
CURRENT R
SHUNT
0.02
V
DD1
V
IN+
V
DD2
MCLK
MDAT
GND2
CCLK
CLAT
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
V
DD
CHAN
SCLK
SDAT
CS
THR1
OVR1
RESET
3-WIRE
SERIAL
INTERFACE
C1
0.1 µF
V
IN-
GND1
C2
0.1 µF
+
C3
10 µF
HCPL-7860
HCPL-x870
Figure 1: Typical Application Circuit.
Product Overview
Description
The HCPL-7860 Isolated Modu-
lator and the HCPL-x870 Digital
Interface IC together form an
isolated programmable two-chip
analog-to-digital converter. The
isolated modulator allows direct
measurement of motor phase
currents in power inverters while
the digital interface IC can be
programmed to optimize the
conversion speed and resolution
trade-off.
In operation, the HCPL-7860
Isolated Modulator (optocoupler
with 3750 V
RMS
dielectric with-
stand voltage rating) converts a
low-bandwidth analog input into
a high-speed one-bit data stream
by means of a sigma-delta (
∑
∆)
oversampling modulator. This
modulation provides for high
noise margins and excellent
immunity against isolation-mode
transients. The modulator data
and on-chip sampling clock are
encoded and transmitted across
the isolation boundary where they
are recovered and decoded into
separate high-speed clock and
data channels.
The Digital Interface IC converts
the single-bit data stream from
the Isolated Modulator into
fifteen-bit output words and
provides a serial output interface
that is compatible with SPI
®
,
QSPI
®
, and Microwire
®
proto-
cols, allowing direct connection
to a microcontroller. The Digital
Interface IC is available in two
package styles: the HCPL-7870 is
in a 16-pin DIP package and the
HCPL-0870 is in a 300-mil wide
SO-16 surface-mount package.
Features of the Digital Interface
IC include five different conver-
sion modes, three different pre-
trigger modes, offset calibration,
fast over-range detection, and
adjustable threshold detection.
Programmable features are con-
figured via the Serial Configura-
tion port. A second multiplexed
input is available to allow
measurements with a second
1-261
isolated modulator without
additional hardware. Because the
two inputs are multiplexed, only
one conversion at a time can be
made and not all features are
available for the second channel.
The available features for both
channels are shown in the table
at right.
HCPL-x870 Digital Interface IC
Feature
Conversion Mode
Offset Calibration
Pre-Trigger Mode
Over-Range Detection
Adjustable Threshold Detection
Channel #1
Channel #2
Functional Diagrams
ISOLATION
BOUNDARY
CCLK
CLAT
1
2
3
4
CH1
CONFIG.
INTER-
FACE
CON-
VERSION
INTER-
FACE
16 V
DD
15 CHAN
V
DD1
V
IN+
V
IN–
GND1
1
2
3
4
8
7
DECODE
V
DD2
MCLK
MDAT
GND2
CDAT
MCLK1
MDAT1
14
SCLK
13
SDAT
12 CS
SIGMA-
DELTA
MOD./
ENCODE
5
6
7
8
CH2
THRES-
HOLD
DETECT
&
RESET
6
5
MCLK2
MDAT2
11 THR1
10
OVR1
9
RESET
SHIELD
GND
HCPL-7860 Isolated Modulator
HCPL-x870 Digital Interface IC
Pin Description, Isolated Modulator
Symbol
V
DD1
V
IN+
V
IN–
GND1
Description
Supply voltage input (4.5 V to 5.5 V)
Positive input (± 200 mV
recommended)
Negative input
(normally connected to GND1)
Input ground
Symbol
V
DD2
MCLK
MDAT
GND2
Description
Supply voltage input (4.5 V to 5.5 V)
Clock output (10 MHz typical)
Serial data output
Output ground
1-262
Pin Description, Digital Interface IC
Symbol
Description
CCLK Clock input for the Serial Configuration
Interface (SCI). Serial Configuration
data is clocked in on the rising edge
of CCLK.
CLAT Latch input for the Serial Configuration
Interface (SCI). The last 8 data bits
clocked in on CDAT by CCLK are
latched into the appropriate
configuration register on the rising
edge of CLAT.
CDAT Data input for the Serial Configuration
Interface (SCI). Serial configuration
data is clocked in MSB first.
MCLK1 Channel 1 Isolated Modulator clock
input. Input Data on MDAT1 is clocked
in on the rising edge of MCLK1.
Symbol
Description
V
DD
Supply voltage (4.5 V to 5.5 V).
CHAN
Channel select input. The input level on
CHAN determines which channel of
data is used during the next conversion
cycle. An input low selects channel 1,
a high selects channel 2.
Serial clock input. Serial data is clocked
out of SDAT on the falling edge of SCLK.
Serial data output. SDAT changes from
high impedance to a logic low output
at the start of a conversion cycle.
SDAT then goes high to indicate that
data is ready to be clocked out. SDAT
returns to a high-impedance state after
all data has been clocked out and CS
has been brought high.
Conversion start input. Conversion
begins on the falling edge of CS. CS
should remain low during the entire
conversion cycle and then be brought
high to conclude the cycle.
Continuous, programmable-threshold
detection for channel 1 input data. A
high level output on THR1 indicates
that the magnitude of the channel 1
input signal is beyond a user
programmable threshold level between
160 mV and 310 mV. This signal
continuously monitors channel 1
independent of the channel select
(CHAN) signal.
High speed continuous over-range
detection for channel 1 input data. A
high level output on OVR1 indicates
that the magnitude of the channel 1
input is beyond full-scale. This signal
continuously monitors channel 1
independent of the CHAN signal.
Master reset input. A logic high input
for at least 100 ns asynchronously
resets all configuration registers to
their default values and zeroes the
Offset Calibration registers.
SCLK
SDAT
MDAT1
Channel 1 Isolated Modulator data
input.
CS
MCLK2
Channel 2 Isolated Modulator clock
input. Input Data on MDAT2 is clocked
in on the rising edge of MCLK2.
THR1
MDAT2
Channel 2 Isolated Modulator data
input.
OVR1
GND
Digital ground.
RESET
1-263
Isolated A/D Converter Performance
Electrical Specifications
Unless otherwise noted, all specifications are at V
IN+
= -200 mV to +200 mV and V
IN-
= 0 V; all Typical
specifications are at T
A
= 25°C and V
DD1
= V
DD2
= V
DD
= 5 V; all Minimum/Maximum specifications are at
T
A
= -40°C to +85°C, V
DD1
= V
DD2
= V
DD
= 4.5 to 5.5 V.
Parameter
Resolution
Integral Nonlinearity
Symbol
Min.
15
INL
6
0.025
1
4
0.7
326
30
0.14
1
2.5
Typ.
Max.
Units
bits
LSB
%
LSB
mV
µV/ °C
mV/V
mV
%
%
ppm/°C
%
mV
Test Conditions
Fig. Note
1
2
3
V
IN+
= 0 V
5
4
STATIC CONVERTER CHARACTERISTICS
3
4
Differential Nonlinearity
DNL
Uncalibrated Input Offset
V
OS
-1
Offset Drift vs. Temperature
dV
OS
/dT
A
Offset drift vs. V
DD1
dV
OS
/dV
DD1
Internal Reference Voltage
V
REF
Absolute Reference Voltage
-4
Tolerance
Reference Voltage
-1
Matching
V
REF
Drift vs. Temperature dV
REF
/dT
A
V
REF
Drift vs. V
DD1
dV
REF
/dV
DD1
Full Scale Input Range
-V
REF
Recommended Input
-200
Voltage Range
4
1
190
0.9
+V
REF
+200
6
T
A
= 25°C.
See Note 5
5
6
DYNAMIC CONVERTER CHARACTERISTICS
(Digital Interface IC is set to Conversion Mode 3.)
Signal-to-Noise Ratio
Total Harmonic Distortion
Signal-to-(Noise
+ Distortion)
Effective Number of Bits
Conversion Time
SNR
THD
SND
ENOB
t
C2
t
C1
t
C0
t
DSIG
t
OVR1
t
THR1
BW
CMR
62
73
-67
66
12
0.7
18
37
18
2.7
10
22
20
dB
V
IN+
= 35 Hz,
400 mV
pk-pk
(141 mV
rms
) sine
wave.
2,9
10
Signal Delay
Over-Range Detect Time
Threshold Detect Time
Signal Bandwidth
Isolation Transient
Immunity
2.0
18
15
1.0
22
44
22
4.2
bits
µs
8
Pre-Trigger Mode 2 7,
Pre-Trigger Mode 1 14
Pre-Trigger Mode 0
10
V
IN+
= 0 to 400 mV 12
step waveform
11
V
ISO
= 1 kV
7
8
kHz
kV/µs
9
10
11
12
13
1-264
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