Preliminary Information
CAT24FC256
256K-Bit I
2
C Serial CMOS EEPROM
FEATURES
I
Fast mode I
2
C bus compatible*
I
Max clock frequency:
I
Industrial and automotive
H
LOGEN
FR
A
EE
LE
temperature ranges
I
5 ms max write cycle time
I
Write protect feature
A
D
F
R
E
E
TM
- 400kHz for V
CC
= 1.8 V to 5.5 V
- 1MHz for V
CC
= 2.5 V to 5.5 V
I
Schmitt trigger filtered inputs for noise suppression
I
Low power CMOS technology
I
64-byte page write buffer
I
Self-timed write cycle with auto-clear
– Entire array protected when WP at V
IH
I
100,000 program/erase cycles
I
100 year data retention
I
8-pin DIP or 8-pin SOIC(JEDEC) and 8-pin SOIC
(EIAJ)
DESCRIPTION
The CAT24FC256 is a 256K-bit Serial CMOS EEPROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC256
features a 64-byte page write buffer. The device oper-
ates via the I
2
C bus serial interface and is available in 8-
pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
SENSE AMPS
SHIFT REGISTERS
SOIC Package (J, W, K, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SDA
START/STOP
LOGIC
XDEC
WP
CONTROL
LOGIC
512
EEPROM
512X512
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
NC
Function
Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
No Connect
A0
A1
A2
SLAVE
ADDRESS
COMPARATORS
SCL
STATE COUNTERS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1040, Rev. F
CAT24FC256
Preliminary Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
Latch-up
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Reference Test Method
MIL-STD-883, Test Method 1008
JEDEC Standard 17
Min
100
100
Typ
Max
Units
Cycles/Byte
Years
mA
MIL-STD-883, Test Method 1033 100,000
DC OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current - Read
Power Supply Current - Write
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= +3.0 V)
Output Low Voltage (V
CC
= +1.8 V)
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100kHz
V
CC
= 5V
f
SCL
= 400kHz
V
CC
= 5V
V
IN
= GND or V
CC
V
CC
= 5V
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-0.5
V
CC
x 0.7
Min
Typ
Max
400
3
0
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
µA
mA
µA
µA
µA
V
V
V
V
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
C
I/O(3)
C
IN(3)
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby current (I
SB
) = 0
µA
(<900 nA).
Doc. No. 1040, Rev. F
2
Preliminary Information
AC CHARACTERISTICS
V
CC
= 1.8V to 5.5 V, unless otherwise specified. Output load is 1 TTL gate and 100pF.
Read & Write Cycle Limits
CAT24FC256
V
CC
= 1.8 V - 5.5 V
Symbol
f
SCL
t
AA
t
BUF(2)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(2)
t
F(2)
t
SU:STO
t
DH
t
WR
t
SP
t
SU:WP
t
HD:WP
Parameter
Clock Frequency
SCL Low to SDA Data Out and
ACK Out
Time the bus must be free before
a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Stup Time (for a
Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppression (SDA, SCL)
WP Setup Time
WP Hold Time
0.6
1.3
0.05
1.3
0.6
1.3
0.6
0.6
0
100
20
20
0.6
50
5
50
0.3
300
Min
Max
400
0.9
V
CC
= 2.5 V - 5.5 V
Min
Max
1000
0.05
0.5
0.25
0.6
0.4
0.25
0
100
0.1
100
0.25
50
5
50
0.5
0.8
0.550
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
ns
µs
µs
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1040, Rev. F
CAT24FC256
Preliminary Information
FUNCTIONAL DESCRIPTION
The CAT24FC256 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC256 operates
as a Slave device. Both the Master device and Slave
device can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC256's may be addressed
on a single bus system. When the pins are left
unconnected, the default values are zero.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
5020 FHD F03
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
5020 FHD F05
Doc. No. 1040, Rev. F
4
Preliminary Information
CAT24FC256
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC256 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
as many as eight devices on the same bus. These bits
must compare to their hardwired input pins. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC256 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC256 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24FC256 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24FC256 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24FC256 will continue to transmit
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC256 uses the next three bits
as address bits. The address bits A2, A1 and A0 allow
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
5
Doc. No. 1040, Rev. F
FPGA/CPLD
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