INTEGRATED CIRCUITS
CBT6832D
16-bit controlled enable rate
1-of-2 multiplexer/demultiplexer
with precharged outputs and charge pump
undershoot protection for live insertion
Product specification
Supersedes data of 2000 May 18
2000 Sep 01
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit controlled enable rate 1-of-2 multiplexer/demultiplexer with precharged
outputs and charge pump undershoot protection for live insertion
CBT6832D
FEATURES
•
5
Ω
typical r
on
•
Pull-up on B port
•
Undershoot protection on A port only: –2.0 V
•
Near zero propagation delay
•
Controlled enable rate
•
V
CC
operating range: +4.5 V to +5.5 V
•
> 100 MHz bandwidth (or clock rate) at 20 pF load capacitance
•
56-pin TSSOP package
•
Bias voltage pre-charges the B output when the channel is
disabled
PIN CONFIGURATION
1B1 1
2B1
2A
3B1
4B1
4A
5B1
6B1
6A
2
3
4
5
6
7
8
9
56 1A
55 1B2
54 2B2
53 3A
52 3B2
51 4B2
50 5A
49 5B2
48 6B2
47 7A
46 7B2
45 8B2
44 GND
43 V
CC
42 9A
41 9B2
40 10B2
39 11A
38 11B2
37 12B2
36 13A
35 13B2
34 14B2
33 15A
32 15B2
31 16B2
30 V
BIAS2
29 SEL2
7B1 10
8B1 11
8A 12
GND 13
V
CC
14
9B1 15
•
Latch-up protection exceeds 100 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
APPLICATION
10B1 16
10A 17
11B1 18
12B1 19
•
Provides PCI-X hot-plugging
DESCRIPTION
The CBT6832D is a 16-bit controlled enable rate 1-of-2
multiplexer/demultiplexer with precharged outputs and charge pump
undershoot protection for live insertion. Advantages of the CBT6832
include a propagation delay of 250 ps, resulting from 5
Ω
channel
resistance, and low I/O capacitance. A port demultiplexes to either
1B and 2B, or to both. The switch is bi-directional.
12A 20
13B1 21
14B1 22
14A 23
15B1 24
16B1 25
16A 26
V
BIAS1
27
SEL1 28
SW00478
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OFF B
C
OFF A
C
ON 1
C
ON 2
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance
B capacitance, switch off
A capacitance, switch off
One channel enabled capacitance
Both channels enabled capacitance
CONDITIONS
T
amb
= 25°C; GND = 0 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
Outputs disabled; V
O
= 0 V
Outputs disabled; V
O
= 0 V
One B enabled; V
O
= 0 V
Both B channels enabled; V
O
= 0 V
TYPICAL
0.25
4.5
8
13
21
34
UNIT
ns
pF
pF
pF
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
0°C to +70°C
ORDER CODE
CBT6832D DGG
DWG NUMBER
SOT364-1
2000 Sep 01
2
853-2216 24481
Philips Semiconductors
Product specification
16-bit controlled enable rate 1-of-2 multiplexer/demultiplexer with precharged
outputs and charge pump undershoot protection for live insertion
CBT6832D
PIN DESCRIPTION
PIN NUMBER
3, 6, 9, 12, 17,
20, 23, 26, 33,
36, 39, 42, 47,
50, 53, 56
1, 2, 4, 5, 7, 8,
10, 11, 15, 16,
18, 19, 21, 22,
24, 25
31, 32, 34, 35,
37, 38, 40, 41,
45, 46, 48, 49,
51, 52, 54, 55
27, 30
28, 29
13, 44
14, 43
SYMBOL
1A1–16A1
NAME AND FUNCTION
LOGIC DIAGRAM
V
BIAS1
Inputs
PULLUP
1A
V
BIAS2
1B1
1B1–16B1
Outputs
PULLUP
1B2–16B2
V
BIAS1
,
V
BIAS2
SEL1, SEL2
GND
V
CC
Outputs
1B2
V
BIAS1
Precharge bias voltage inputs
Select-control inputs
Ground (0 V)
Positive supply voltage
16A
PULLUP
V
BIAS2
16B1
PULLUP
16B2
FUNCTION TABLE
SEL1
L
H
L
H
SEL2
H
L
L
H
nA to nB1
nA to nB2
nA to nB1 and nB2
nB1, nB2 = V
BIAS
SV01801
SEL2
FUNCTION
SEL1
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output voltage
3
DC output current
Storage temperature range
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–50
–0.5 to +7.0
–0.5 to +7.0
120
–65 to +150
UNIT
V
mA
V
V
mA
°C
Θ
JA
Power dissipation
95
°C/W
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
T
amb
DC supply voltage
High-level input voltage
Low-level Input voltage
Operating free-air temperature range
0
PARAMETER
LIMITS
MIN
4.5
2.0
0.8
+70
MAX
5.5
UNIT
V
V
V
°C
2000 Sep 01
3
Philips Semiconductors
Product specification
16-bit controlled enable rate 1-of-2 multiplexer/demultiplexer with precharged
outputs and charge pump undershoot protection for live insertion
CBT6832D
DC ELECTRICAL CHARACTERISTICS
Over operating temperature range T
amb
= 0°C to +70°C; V
CC
= 5 V
±10%;
V
BIAS
= 1.3 V to V
CC
, unless otherwise specified.
SYMBOL
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
r
on
PARAMETER
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
High impedance output current
Low impedance output current
Input clamp voltage
Switch on resistance
2
TEST CONDITIONS
Guaranteed logic HIGH level
Guaranteed logic LOW level
V
CC
= 5.5 V, V
IN
= V
CC
V
CC
= 5.5 V, V
IN
= GND
A = 0 V or V
CC
MAX,
V
BIAS1
= V
BIAS2
= V
CC
MAX
B = 0 V or V
CC
MAX,
V
BIAS1
= V
BIAS2
= V
CC
MAX
V
CC
= 4.5 V; I
I
= –18 mA
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 48 mA
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
= –15 mA
V
I
= 0 V
V
I
= 0 V
V
I
= 0 V
V
I
= 0 V
V
I
= 0 V
V
CC
= 5.5 V; V
I
= V
CC
or GND
V
CC
= 5.5 V, one input at 3.4 V,
other inputs at V
CC
or GND
–0.2
–0.7
5
10
4.5
8
13
21
34
200
2.5
LIMITS
MIN
2.0
–0.5
0.8
±5
±5
±1
–2
–1.8
8
15
TYP
1
MAX
UNIT
V
V
µA
µA
µA
mA
V
Ω
Ω
pF
pF
pF
pF
pF
µA
mA
Capacitance
3
(T
amb
= +25°C; f = 1 MHz)
C
IN
C
OFF B
C
OFF A
C
ON 1
C
ON 2
I
CC
∆I
CC
Input capacitance
B capacitance, switch off
A capacitance, switch off
Capacitance, switch on (one B)
Capacitance, both B channels enabled
Quiescent supply current enabled
Additional supply current per input pin
5
Power supply
NOTES:
1. All typical values are at V
CC
= 5 V, T
amb
= +25°C ambient and maximum loading.
2. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
3. These parameters are determined by device characterization, but is not production tested.
4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
5. Per TTL driven input (V
I
= 3.4 V, control inputs only); A and B pins do not contribute to I
CC
.
6. This current applies to the control inputs only and represent the current required to switch internal capacitance at the specified frequency.
The A and B inputs generate no significant AC or DC currents as they transition. this parameter is not tested, but is guaranteed by design.
2000 Sep 01
4
Philips Semiconductors
Product specification
16-bit controlled enable rate 1-of-2 multiplexer/demultiplexer with precharged
outputs and charge pump undershoot protection for live insertion
CBT6832D
AC CHARACTERISTICS
V
CC
= 5.0 V
±0.5
V; GND = 0 V
;
C
L
= 50 pF, R
L
= 500
Ω
SYMBOL
t
PLH
t
PHL
t
PZH
t
PZL
PARAMETER
Propagation delay
1
A to B
Bus enable time
SEL to A, B
10
5
TEST CONDITIONS
LIMITS
MIN
TYP
0.25
30
25
MAX
UNIT
ns
ns
t
PHZ
Bus disable time
0.5
6
ns
t
PLZ
SEL to A, B
0.5
7
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
3V
1.5V
INPUT
0V
t
PLH
t
PHL
V
OH
1.5V
OUTPUT
V
OL
1.5V
1.5V
TEST CIRCUIT AND WAVEFORMS
7V
From Output
Under Test
C
L
= 50 pF
500
Ω
S1
Open
GND
500
Ω
Load Circuit
TEST
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
open
7V
open
SA00028
Waveform 1. Input (An) to Output (Bn) Propagation Delays
DEFINITIONS
Load capacitance includes jig and probe capacitance;
C
L
=
see AC CHARACTERISTICS for value.
Output Control
(Low-level
enabling
t
PZL
Output
Waveform 1
S1 at 7 V
(see Note)
t
PZH
Output
Waveform 2
S1 at Open
(see Note)
3V
1.5 V
1.5 V
0V
3.5V
1.5 V
t
PHZ
V
OH
– 0.3V
1.2 V
0V
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
SA00012
t
PLZ
V
OL
+ 0.3V
V
OL
V
OH
SA00543
Waveform 2. 3-State Output Enable and Disable Times
2000 Sep 01
5
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