Philips Semiconductors
Product specification
Triacs
logic level
GENERAL DESCRIPTION
Passivated, sensitive gate triacs in a
plastic envelope suitable for surface
mounting, intended for use in general
purpose bidirectional switching and
phase control applications. These
devices are intended to be interfaced
directly to microcontrollers, logic
integrated circuits and other low power
gate trigger circuits.
BT136S series D
QUICK REFERENCE DATA
SYMBOL
V
DRM
I
T(RMS)
I
TSM
PARAMETER
BT136S
-
Repetitive peak off-state
voltages
RMS on-state current
Non-repetitive peak on-state current
MAX.
600D
600
4
25
UNIT
V
A
A
PINNING - SOT428
PIN
1
2
3
tab
DESCRIPTION
MT1
MT2
gate
MT2
PIN CONFIGURATION
tab
SYMBOL
T2
T1
2
1
3
G
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
V
DRM
I
T(RMS)
I
TSM
PARAMETER
Repetitive peak off-state
voltages
RMS on-state current
Non-repetitive peak
on-state current
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
full sine wave; T
mb
≤
107 ˚C
full sine wave; T
j
= 25 ˚C prior to
surge
t = 20 ms
t = 16.7 ms
t = 10 ms
I
TM
= 6 A; I
G
= 0.2 A;
dI
G
/dt = 0.2 A/µs
T2+ G+
T2+ G-
T2- G-
T2- G+
CONDITIONS
MIN.
-
-
-
-
-
-
-
-
-
-
-
-
-
-40
-
MAX.
-600
600
4
25
27
3.1
50
50
50
10
2
5
5
0.5
150
125
UNIT
V
A
A
A
A
2
s
A/µs
A/µs
A/µs
A/µs
A
V
W
W
˚C
˚C
I
2
t
dI
T
/dt
I
GM
V
GM
P
GM
P
G(AV)
T
stg
T
j
Peak gate current
Peak gate voltage
Peak gate power
Average gate power
Storage temperature
Operating junction
temperature
over any 20 ms period
June 2001
1
Rev 1.300
Philips Semiconductors
Product specification
Triacs
logic level
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
CONDITIONS
MIN.
-
-
-
BT136S series D
TYP.
-
-
75
MAX.
3.0
3.7
-
UNIT
K/W
K/W
K/W
Thermal resistance
full cycle
junction to mounting base half cycle
Thermal resistance
pcb (FR4) mounted; footprint as in Fig.14
junction to ambient
STATIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
I
GT
PARAMETER
Gate trigger current
CONDITIONS
V
D
= 12 V; I
T
= 0.1 A
T2+ G+
T2+ G-
T2- G-
T2- G+
T2+ G+
T2+ G-
T2- G-
T2- G+
MIN.
-
-
-
-
-
-
-
-
-
-
-
0.25
-
TYP.
2.0
2.5
2.5
5.0
1.6
4.5
1.2
2.2
1.2
1.4
0.7
0.4
0.1
MAX.
5
5
5
10
10
15
10
15
10
1.70
1.5
-
0.5
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
mA
I
L
Latching current
V
D
= 12 V; I
GT
= 0.1 A
I
H
V
T
V
GT
I
D
Holding current
On-state voltage
Gate trigger voltage
Off-state leakage current
V
D
= 12 V; I
GT
= 0.1 A
I
T
= 5 A
V
D
= 12 V; I
T
= 0.1 A
V
D
= 400 V; I
T
= 0.1 A; T
j
= 125 ˚C
V
D
= V
DRM(max)
; T
j
= 125 ˚C
DYNAMIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
dV
D
/dt
t
gt
PARAMETER
Critical rate of rise of
off-state voltage
Gate controlled turn-on
time
CONDITIONS
V
DM
= 67% V
DRM(max)
; T
j
= 125 ˚C;
exponential waveform; R
GK
= 1 kΩ
I
TM
= 6 A; V
D
= V
DRM(max)
; I
G
= 0.1 A;
dI
G
/dt = 5 A/µs
MIN.
-
-
TYP.
5
2
MAX.
-
-
UNIT
V/µs
µs
June 2001
2
Rev 1.300
Philips Semiconductors
Product specification
Triacs
logic level
BT136S series D
8
7
6
5
4
3
2
1
0
Ptot / W
Tmb(max) / C
101
104
5
IT(RMS) / A
1
= 180
120
90
60
30
107
110
113
116
119
4
107 C
3
2
1
122
0
1
2
3
IT(RMS) / A
4
125
5
0
-50
0
50
Tmb / C
100
150
Fig.1. Maximum on-state dissipation, P
tot
, versus rms
on-state current, I
T(RMS)
, where
α
= conduction angle.
Fig.4. Maximum permissible rms current I
T(RMS)
,
versus mounting base temperature T
mb
.
IT(RMS) / A
1000
ITSM / A
IT
T
ITSM
12
10
time
Tj initial = 25 C max
100
dI
T
/dt limit
8
6
4
T2- G+ quadrant
2
10
10us
100us
1ms
T/s
10ms
100ms
0
0.01
0.1
1
surge duration / s
10
Fig.2. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus pulse width t
p
, for
sinusoidal currents, t
p
≤
20ms.
Fig.5. Maximum permissible repetitive rms on-state
current I
T(RMS)
, versus surge duration, for sinusoidal
currents, f = 50 Hz; T
mb
≤
107˚C.
VGT(Tj)
VGT(25 C)
30
25
20
15
10
5
0
ITSM / A
BT136
1.6
IT
T
I TSM
time
1.4
1.2
1
0.8
0.6
0.4
-50
Tj initial = 25 C max
1
10
100
Number of cycles at 50Hz
1000
0
50
Tj / C
100
150
Fig.3. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
Fig.6. Normalised gate trigger voltage
V
GT
(T
j
)/ V
GT
(25˚C), versus junction temperature T
j
.
June 2001
3
Rev 1.300
Philips Semiconductors
Product specification
Triacs
logic level
BT136S series D
3
2.5
2
1.5
1
0.5
IGT(Tj)
IGT(25 C)
T2+ G+
T2+ G-
T2- G-
T2- G+
12
10
IT / A
Tj = 125 C
Tj = 25 C
Vo = 1.27 V
Rs = 0.091 ohms
typ
max
8
6
4
2
0
0
-50
0
50
Tj / C
100
150
0
0.5
1
1.5
VT / V
2
2.5
3
Fig.7. Normalised gate trigger current
I
GT
(T
j
)/ I
GT
(25˚C), versus junction temperature T
j
.
IL(Tj)
IL(25 C)
Fig.10. Typical and maximum on-state characteristic.
10
Zth j-mb (K/W)
unidirectional
bidirectional
3
2.5
1
2
1.5
1
0.5
0
-50
0.01
10us
0.1ms
1ms
10ms
tp / s
0.1s
1s
0.1
P
D
tp
t
0
50
Tj / C
100
150
10s
Fig.8. Normalised latching current I
L
(T
j
)/ I
L
(25˚C),
versus junction temperature T
j
.
IH(Tj)
IH(25C)
Fig.11. Transient thermal impedance Z
th j-mb
, versus
pulse width t
p
.
dVD/dt (V/us)
1000
3
2.5
2
1.5
1
0.5
100
10
0
-50
0
50
Tj / C
100
150
1
0
50
Tj / C
100
150
Fig.9. Normalised holding current I
H
(T
j
)/ I
H
(25˚C),
versus junction temperature T
j
.
Fig.12. Typical, critical rate of rise of off-state voltage,
dV
D
/dt versus junction temperature T
j
.
June 2001
4
Rev 1.300
Philips Semiconductors
Product specification
Triacs
logic level
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.1 g
6.73 max
1.1
2.38 max
0.93 max
seating plane
BT136S series D
5.4
tab
4 min
6.22 max
10.4 max
4.6
2
1
2.285 (x2)
0.5 min
0.5
0.3
0.5
3
0.8 max
(x2)
Fig.13. SOT428 : centre pin connected to tab.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.14. SOT428 : minimum pad sizes for surface mounting.
Notes
1. Plastic meets UL94 V0 at 1/8".
June 2001
5
Rev 1.300
模拟电子
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