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SN74AUC1G00
SINGLE 2 INPUT POSITIVE NAND GATE
SCES368M − SEPTEMBER 2001 − REVISED MAY 2005
D
Available in the Texas Instruments
D
D
D
D
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max t
pd
of 2.2 ns at 1.8 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
D
Low Power Consumption, 10-µA Max I
CC
D
±8-mA
Output Drive at 1.8 V
D
Latch-Up Performance Exceeds 100 mA Per
D
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
A
B
GND
1
5
V
CC
A
B
1
2
3
5
V
CC
A
B
GND
1
2
3
5
V
CC
Y
GND
B
A
3 4
2
1 5
Y
V
CC
2
4
GND
4
4
Y
3
Y
See mechanical drawings for dimensions.
description /ordering information
This single 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for
1.65-V to 1.95-V V
CC
operation.
The SN74AUC1G00 performs the Boolean function Y = A
•
B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PACKAGE†
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
SOT (SOT-553) − DRL
Tape and reel
Tape and reel
Reel of 4000
Tape and reel
SN74AUC1G00YEPR
SN74AUC1G00YZPR
SN74AUC1G00DBVR
SN74AUC1G00DCKR
SN74AUC1G00DRLR
U00_
UA_
UA_
ORDERABLE PART NUMBER
SN74AUC1G00YEAR
SN74AUC1G00YZAR
_ _ _UA_
TOP-SIDE MARKING‡
−40°C to 85°C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN74AUC1G00
SINGLE 2 INPUT POSITIVE NAND GATE
SCES368M − SEPTEMBER 2001 − REVISED MAY 2005
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report,
Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices,
literature number SCEA027.
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
logic diagram (positive logic)
A
B
1
2
4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±100
mA
Package thermal impedance,
θ
JA
(see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74AUC1G00
SINGLE 2 INPUT POSITIVE NAND GATE
SCES368M − SEPTEMBER 2001 − REVISED MAY 2005
recommended operating conditions (see Note 3)
MIN
VCC
VIH
Supply voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
VI
VO
Low-level input voltage
Input voltage
Output voltage
VCC = 0.8 V
VCC = 1.1 V
IOH
High-level output current
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
IOL
Low-level output current
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
∆t/∆v
Input transition rise or fall rate
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0
0
0.8
VCC
0.65
×
VCC
1.7
0
0.35
×
VCC
0.7
3.6
VCC
−0.7
−3
−5
−8
−9
0.7
3
5
8
9
20
10
ns/V
mA
mA
V
V
V
MAX
2.7
UNIT
V
High-level input voltage
V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = −100
µA
IOH = −0.7 mA
VOH
IOH = −3 mA
IOH = −5 mA
IOH = −8 mA
IOH = −9 mA
IOL = 100
µA
IOL = 0.7 mA
VOL
IOL = 3 mA
IOL = 5 mA
IOL = 8 mA
IOL = 9 mA
II
Ioff
ICC
Ci
A or B input
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
TEST CONDITIONS
VCC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
3
0.25
0.3
0.4
0.45
0.6
±5
±10
10
µA
µA
µA
pF
V
0.8
1
1.2
1.8
0.2
V
MIN
VCC−0.1
0.55
TYP†
MAX
UNIT
† All typical values are at TA = 25°C.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN74AUC1G00
SINGLE 2 INPUT POSITIVE NAND GATE
SCES368M − SEPTEMBER 2001 − REVISED MAY 2005
switching characteristics over recommended operating free-air temperature range, C
L
= 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
VCC = 0.8 V
TYP
4.7
VCC = 1.2 V
±
0.1 V
MIN
0.9
MAX
3.2
VCC = 1.5 V
±
0.1 V
MIN
0.5
MAX
2.2
VCC = 1.8 V
±
0.15 V
MIN
†
TYP
†
MAX
†
VCC = 2.5 V
±
0.2 V
MIN
†
MAX
†
ns
UNIT
† This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range, C
L
= 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
VCC = 1.8 V
±
0.15 V
MIN
0.7
TYP
1.3
MAX
2.2
VCC = 2.5 V
±
0.2 V
MIN
0.5
MAX
2
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
15
VCC = 1.2 V
TYP
15
VCC = 1.5 V
TYP
15
VCC = 1.8 V
TYP
15
VCC = 2.5 V
TYP
19
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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