NAND FLASH
528 Byte, 264 Word Page Family
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
1.8V, 3V Supply Flash Memories
DATA BRIEFING
FEATURES SUMMARY
s
HIGH DENSITY NAND FLASH MEMORIES
– Up to 1 Gbit memory array
– Up to 32Mbit spare area
– Cost effective solutions for mass storage ap-
plications
s
Figure 1. Packages
NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
TSOP48
12 x 20 mm
s
SUPPLY VOLTAGE
– 1.8V device: V
CC
= 1.65 to 1.95V
– 3.0V device: V
CC
= 2.7 to 3.6V
FBGA
s
PAGE SIZE
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
VFBGA63 8.5x15x1 mm
TFBGA63 8.5x15x1.2 mm
VFBGA63 9x11x1 mm
s
BLOCK SIZE
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
s
AUTOMATIC PAGE 0 READ AT POWER-UP
OPTION
– Boot from NAND support
– Automatic Memory Download
s
PAGE READ / PROGRAM
– Random access: 12µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
s
s
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
– Program/Erase locked during Power transi-
tions
s
COPY BACK PROGRAM MODE
– Fast page copy without external buffering
CACHE PROGRAM MODE
– Internal Cache Register to improve the pro-
gram throughput
s
s
DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
s
FAST BLOCK ERASE
– Block erase time: 2ms (Typ)
STATUS REGISTER
ELECTRONIC SIGNATURE
CHIP ENABLE ‘DON’T CARE’ OPTION
– Simple interface with microcontroller
s
DEVELOPMENT TOOLS
– Error Correction Code software and hard-
ware models
– Bad Blocks Management and Wear Leveling
algorithms
– PC Demo board with simulation software
– File System OS Native reference software
– Hardware simulation models
s
s
s
August 2003
For further information please contact the STMicroelectronics distributor nearest to you.
1/5
NAND FLASH, 528 Byte, 264 Word Page Family
SUMMARY DESCRIPTION
The NAND Flash 528 Byte/ 264 Word Page is a
family of non-volatile Flash memories that uses
NAND cell technology. The devices range from
128Mbits to 1Gbit and operate with either a 1.8V
or 3V voltage supply. The size of a Page is either
528 Bytes (512 + 16 spare) or 264 Words (256 + 8
spare) depending on whether the device has a x8
or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
put/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC). A Write
Protect pin is available to give a hardware protec-
tion against program and erase operations.
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back command is available to optimize the
management of defective blocks. When a Page
Program operation fails, the data can be pro-
grammed in another page without having to re-
send the data to be programmed.
Each device has a Cache Program feature which
improves the program throughput for large files. It
loads the data in a Cache Register while the pre-
Table 1. Product List
Timings
Part Number
Density
Bus
Width
Page Size
Block Size
Memory
Array
Operating
Voltage
1.65 to 1.95V
32 Pages x
1024 Blocks
2.7 to 3.6V
1.65 to 1.95V
2.7 to 3.6V
1.65 to 1.95V
32 Pages x
2048 Blocks
2.7 to 3.6V
1.65 to 1.95V
2.7 to 3.6V
1.65 to 1.95V
32 Pages x
4096 Blocks
2.7 to 3.6V
1.65 to 1.95V
2.7 to 3.6V
1.65 to 1.95V
32 Pages x
8192 Blocks
2.7 to 3.6V
1.65 to 1.95V
2.7 to 3.6V
Random
Access
Max
15µs
12µs
15µs
12µs
15µs
12µs
15µs
12µs
15µs
12µs
15µs
12µs
15µs
12µs
15µs
12µs
Sequential
Access
Min
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
Page
Program
Typical
300µs
200µs
300µs
200µs
300µs
200µs
300µs
200µs
300µs
200µs
300µs
200µs
300µs
200µs
300µs
200µs
2ms
2ms
TSOP48
VFBGA63
(8.5x15x1
mm)
2ms
TSOP48
VFBGA63
(9x11x1 mm)
2ms
TSOP48
VFBGA63
(9x11x1 mm)
Block
Erase
Typical
Package
vious data is transferred to the Page Buffer and
programmed into the memory array.
The devices are available in the following packag-
es:
s
TSOP48 12 x 20mm for all products
s
VFBGA63 (8.5x15x1 mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product
s
TFBGA63 (8.5x15x1.2 mm, 6 x 8 ball array,
0.8mm pitch) for the 1Gb product
s
VFBGA63 (9x15x1 mm, 6 x 8 ball array, 0.8mm
pitch) for 128Mb and 256Mb products.
Three options are available for the NAND Flash
family:
s
Automatic Page 0 Read after Power-up, which
allows the microcontroller to directly download
the boot code from page 0.
s
Chip Enable Don’t Care, which allows code to
be directly downloaded by a microcontroller, as
Chip Enable transitions during the latency time
do not stop the read operation.
s
A Serial Number, which allows each device to
be uniquely identified. The Serial Number
options is subject to an NDA (Non Disclosure
Agreement) and so not described in the
datasheet. For more details of this option
contact your nearest ST Sales office.
For information on how to order these options refer
to Table 3, Ordering Information Scheme. Devices
are shipped from the factory with Block 0 always
valid and the memory content bits, in valid blocks,
erased to ’1’.
See Table 1, Product List, for all the devices avail-
able in the family.
NAND128R3A
NAND128W3A
NAND128R4A
NAND128W4A
NAND256R3A
NAND256W3A
NAND256R4A
NAND256W4A
NAND512R3A
NAND512W3A
NAND512R4A
NAND512W4A
NAND01GR3A
NAND01GW3A
NAND01GR4A
NAND01GW4A
1Gbit
512Mbit
256Mbit
128Mbit
x8
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
512+16
Bytes
256+8
Words
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
16K+512
Bytes
8K+256
Words
x16
x8
x16
x8
x16
x8
x16
TSOP48
TFBGA63
(8.5x15x1.2
mm)
2/5
NAND FLASH, 528 Byte, 264 Word Page Family
Figure 2. Logic Block Diagram
Address
Register/Counter
X Decoder
AL
CL
W
E
WP
R
Command
Interface
Logic
P/E/R Controller,
High Voltage
Generator
NAND Flash
Memory Array
Page Buffer
Command Register
Cache Register
Y Decoder
I/O Buffers & Latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI07561b
Figure 3. Logic Diagram
VCC
Table 2. Signal Names
I/O8-15
I/O0-7
Data Input/Outputs for x16 devices
Data Input/Outputs, Address Inputs,
or Command Inputs for x8 and x16
devices
Address Latch Enable
Command Latch Enable
Chip Enable
Read Enable
Ready/Busy (open-drain output)
Write Enable
Write Protect
Supply Voltage
Ground
Not Connected Internally
Do Not Use
I/O8-I/O15, x16
E
I/O0-I/O7, x8/x16
R
W
AL
CL
WP
NAND Flash
RB
AL
CL
E
R
RB
W
WP
V
CC
V
SS
NC
VSS
AI07557b
DU
3/5
NAND FLASH, 528 Byte, 264 Word Page Family
PART NUMBERING
Table 3. Ordering Information Scheme
Example:
Device Type
NAND Flash Memory
Density
128 = 128Mb
256 = 256Mb
512 = 512Mb
01G = 1Gb
Operating Voltage
R = V
CC
= 1.65 to 1.95V
W = V
CC
= 2.7 to 3.6V
Bus Width
3 = x8
4 = x16
Family Identifier
A = 528 Bytes/ 264 Word Page
Options
0 = normal
1 = Read Page0 at Power-up
2 = Chip Enable Don’t Care
3 = Chip Enable Don’t Care Enabled and Read Page0 at Power-up
Silicon Version
A, B, C, D
Package
N = TSOP48 12 x 20mm
ZA = VFBGA63 9 x 11x1mm, 6x8 ball array, 0.8mm pitch (128Mbit and 256Mbit devices)
ZA = VFBGA63 8.5 x 15x1mm, 6x8 ball array, 0.8mm pitch (512Mbit devices)
ZA = TFBGA63 8.5 x 15x1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit devices)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
E = Lead Free Package, Standard Packing
F = Lead Free Package, Tape & Reel Packing
NAND512R3A
0
A ZA 1
T
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’.
For further information on any aspect of this device, please contact your nearest ST Sales Office.
4/5
NAND FLASH, 528 Byte, 264 Word Page Family
REVISION HISTORY
Table 4. Document Revision History
Date
16-Apr-2003
18-Jun-2003
18-Jul-2003
07-Aug-2003
Version
1.0
1.1
1.2
2.0
First Issue
NAND Databrief updated to first issue of NAND Datasheet (text changes in
FEATURES SUMMARY and SUMMARY DESCRIPTION sections).
NAND Databrief updated to second issue of NAND Datasheet: VFBGA63 9 x 11mm
package added and minor text changes.
NAND Databrief updated to 07-Aug-2003 2.0 issue of NAND Datasheet: minor text
changes to clarify packages.
Revision Details
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta -
Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
5/5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
