NXP Semiconductors
Data Sheet: Technical Data
IMX7ULPCEC
Rev. 0, 06/2019
i.MX 7ULP Applications
Processor—Consumer Products
MCIMX7U5DVP07SC
MCIMX7U5DVK07SC
MCIMX7U3DVK07SC
The i.MX 7ULP product family members are optimized for power-
sensitive applications benefiting from NXP's Heterogeneous
Multicore Processing (HMP) architecture. Achieving an efficient
balance between processing power and deterministic processing
needs, the i.MX 7ULP is an asymmetric processor consisting of
two separate processing domains: an application domain and a
real-time domain. The application domain is built around an
ARM® Cortex®-A7 processor with an ARM NEON™ SIMD
engine and floating point unit (FPU) and is optimized for rich OS
based applications. The real-time domain is built around an ARM
Plastic packages: BGA 14x14mm, 0.5mm pitch,
Cortex-M4 processor (with FPU) optimized for lowest possible
and BGA 10 x 10 mm, 0.5 mm pitch
leakage. Both domains are completely independent, with
separate power, clocking, and peripheral domains, but the bus
fabric of each domain is tightly integrated for efficient
communication. The part is streamlined to minimize pin count, enabling small packages and simple system
integration.
i.MX 7ULP features
Feature type
ARM Processor
Application processor domain
Cortex®-A7
• Nominal (RUN) frequency: 500 MHz
• Overdrive (HSRUN) frequency: 720
MHz
• Very Low Power Run (VLPR)
frequency: 48 MHz
32 KB instruction and data caches
256 KB L2 cache
NEON™ SIMD engine
FPU
On-chip memory
256 KB of RAM
—
External memory
interfaces
Security
16/32-bit LPDDR2/LPDDR3 interface
running at 380 MHz
eMMC 5.0 interface
Secure boot
Real-time processor domain
Cortex®-M4
• Maximum frequency: 200 MHz
• Very Low Power Run (VLPR)
frequency: 48 MHz
Optimized for lowest leakage current
FPU
MPU
—
—
256 KB of tightly coupled RAM allocated into
32 KB switchable blocks
8 KB of OTP memory
Serial flash interface supporting x4 and x8
IOs
—
Secure boot
Table continues on the next page...
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
i.MX 7ULP features (continued)
Feature type
Application processor domain
Signing and encrypt/decrypt engines
(CAAM)
Simple tamper detection
Serial peripherals
Four I2C Fast mode plus
SD 3.0/MMC 5.0
Four UARTs with flow control
Two LPSPI peripherals
Timers
Four 32-bit general-purpose timers with
capture and compare; one 64-bit timer
Watchdog timer
Real-time processor domain
Encrypt/decrypt engines (LTC)
—
Four I2C Fast mode plus
FlexI/O
Four UARTs with flow control
Two LPSPI peripherals
Four 32-bit general purpose-timers with
capture and compare; one 64-bit timer
Watchdog timer
2
NXP Semiconductors
i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019
i.MX 7ULP
Application Domain
Timers
32 bit Timer x4
System timers
Watch Dog
DMA
Internal Memory
256K RAM
32K Secure
Memory
A7 Connectivity
Arm Cortex
-A7
32KB I-cache
32KB D-cache
UART x 4
I
2
C x4
SPI x 2
3.3V/1.8V GPIO
USB2.0 OTG
(w/ PHY)
USB2.0 HOST
(w/ HSIC)
FlexIO
External Memory
16/32-bit LPDDR2/3
MMC5.0/SDIO x 2
FlexBUS
256KB L2 cache
NEON
Trust Zone
Graphics
GC7000
NanoULTRA
Display
MIPI DSI
GC320
Composition
Camera
VIU
FPU
ETM
Security
Crypto / TRNG
HAB – Secure Boot
Secure Fuse
Security
–
Batt Domain
Tamper
Detection
Secure
RTC
Key
Storage
Clock and Power Management System
Power
Manager
Clock/Reset
PLL/OSC
Timers
32 bit Timer x4
System timers
Watch Dog
Access and IPC
XRDC
Secure JTAG
SEMA4 / Msg Unit
Security
uHAB – Secure Boot
eFuses / OTP
Crypto / TRNG
Real Time Domain
Arm Cortex -
M4
-
DSP Extensions
8KB I/D - cache
DAP
MPU
Analog
2x 12 bit ADC
2x 12 -bit DAC
FPU
M4 Connectivity
UART x 4
I
2
C x4
SPI x2
3.3V/1.8V GPIO
I
2
S x 2
FlexIO
External Memory
Quad SPI (OTFAD)
Internal Memory
256K RAM
Analog Comparators
Figure 1. i.MX 7ULP Block Diagram
The following table provides examples of orderable sample part numbers covered by this data sheet.
Ordering information
Part Number
Options
Cortex-
A7
Speed
Grade
Cortex-
M4
Speed
Grade
Qualification
Tier
Junction
Temperature
Range
0 to +95 °C
Package
MCIMX7U5DVP07SC GPU-2D, 720 MHz 200 MHz Commercial
GPU-3D
(Consumer)
supported
14 mm x 14 mm, 0.5 mm
pitch BGA, Package code
"VP"
Table continues on the next page...
i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019
3
NXP Semiconductors
Ordering information (continued)
Part Number
Options
Cortex-
A7
Speed
Grade
Cortex-
M4
Speed
Grade
Qualification
Tier
Junction
Temperature
Range
0 to +95 °C
Package
MCIMX7U5DVK07SC GPU-2D, 720 MHz 200 MHz Commercial
GPU-3D
(Consumer)
supported
MCIMX7U3DVK07SC No GPU
720 MHz 200 MHz Commercial
(Consumer)
10 mm x 10 mm, 0.5 mm
pitch BGA, Package code
"VK"
10 mm x 10 mm, 0.5 mm
pitch BGA, Package code
"VK"
0 to +95 °C
The following figure describes the part number nomenclature so users can identify the characteristics of the
specific part number.
Figure 2. i.MX 7 Family Part Number Definition
Related Resources
Type
Reference Manual
Data Sheet
Chip Errata
Package drawing
Description
The
i.MX 7ULP Applications Processor Reference Manual
contains a comprehensive description of
the structure and function (operation) of the SoC.
The Data Sheet includes electrical characteristics and signal connections.
The chip mask set errata provides additional or corrective information for a particular device mask
set.
Package dimensions are provided in
Package information and contact assignments
4
NXP Semiconductors
i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019
Microchip MCU
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