HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C
HY5W22F-C / HY57W283220T-C
4Banks x 1M x 32bits Synchronous DRAM
DESCRIPTION
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G
cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs
The Hynix HY5W2A2F-C series is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory appli-
cations which require wide data I/O and high bandwidth. HY5W2A2F-C series is organized as 4banks of
1,048,576x32.
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst
length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM
also provides for special programmable options including Partial Array Self Refresh of 1bank, 2banks, or all banks,
Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress
can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write
command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum
power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can
cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line lay-
out flexibility.
FEATURES
•
•
•
•
•
•
Standard SDRAM Protocol
Internal 4bank operation
Voltage : VDD = 2.5V, VDDQ = 1.8V
& 2.5V
LVTTL compatible I/O Interface
Low Voltage interface to reduce I/O power
Low Power Features ( HY5W22FC / HY57W283220T-C series can’t support these features)
- PASR(Partial Array Self Refresh)
- TCSR(Temperature Compensated Self Refresh)
- Deep Power Down Mode
Packages : 90ball, 0.8mm pitch FBGA / 86pin, TSOP
-10 ~ 80C Operation
•
•
ORDERING INFORMATION
Part No.
HY57W2A3220(L/S)T-HC
HY5W2A2(L/S)F-HC
HY57W2A3220(L/S)T-8C
HY5W2A2(L/S)F-8C
HY57W2A3220(L/S)T-PC
HY5W2A2(L/S)F-PC
HY57W2A3220(L/S)T-SC
HY5W2A2(L/S)F-SC
HY57W2A3220(L/S)T-BC
HY5W2A2(L/S)F-BC
Clock Frequency
CAS Latench
133MHz
CL 3
125MHz
CL 3
100MHz
CL 2
100MHz
CL 3
66MHz
CL 2
Organization
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
Interface
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Package
90balls FBGA
(HY5xxxxxxF)
86pin TSOP-II
(HY5xxxxxxT)
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5/Nov. 02
HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C
HY5W22CF-C / HY57W283220T-C
4Banks x 1M x 32bits Synchronous DRAM
PIN CONFIGURATION ( HY57W2A3220T-C Series)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DD
DQM0
/W E
/C A S
/R A S
/C S
A11
BA0
BA1
A 1 0 /A P
A0
A1
A2
DQM2
V
DD
NC
D Q 16
V
SSQ
D Q 17
D Q 18
V
DDQ
D Q 19
D Q 20
V
SSQ
D Q 21
D Q 22
V
DDQ
D Q 23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
D Q 15
V
SSQ
D Q 14
D Q 13
V
DDQ
D Q 12
D Q 11
V
SSQ
D Q 10
DQ9
V
DDQ
DQ8
NC
V
SS
DQM1
NC
NC
C LK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
D Q 31
V
DDQ
D Q 30
D Q 29
V
SSQ
D Q 28
D Q 27
V
DDQ
D Q 26
D Q 25
V
SSQ
D Q 24
V
SS
8 6 p in T S O P II
4 0 0 m il x 8 7 5 m il
0 .5 m m p in p itc h
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.5/Nov. 02
3
HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C
HY5W22CF-C / HY57W283220T-C
4Banks x 1M x 32bits Synchronous DRAM
Ball CONFIGURATION ( HY5W2A2F-C Series)
1
A
D Q 26
D Q 24
VSS
VDD
D Q 23
D Q 21
2
3
4
5
6
7
8
9
B
D Q 28
VDDQ
VSSQ
VDDQ
VSSQ
D Q 19
C
VSSQ
D Q 27
D Q 25
D Q 22
D Q 20
VDDQ
D
VSSQ
D Q 29
D Q 30
D Q 17
D Q 18
VDDQ
E
VDDQ
D Q 31
NC
NC
D Q 16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A 10
A0
A1
H
A7
A8
NC
T o p V ie w
NC
BA1
A 11
J
C LK
CKE
A9
BA0
/C S
/R A S
K
DQM1
NC
NC
/C A S
/W E
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
D Q 10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
D Q 12
D Q 14
DQ1
DQ3
VDDQ
P
D Q 11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
D Q 13
D Q 15
VSS
VDD
DQ0
DQ2
Ball DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.5/Nov. 02
4
HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C
HY5W22CF-C / HY57W283220T-C
4Banks x 1M x 32bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
TCSR, PASR
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
State Machine
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row
Active
Row
Pre
Decoders
1Mx32 Bank3
1Mx32 Bank2
1Mx32 Bank1
1Mx32 Bank0
Row decoders
Row decoders
Row decoders
Row decoders
Sense AMP & I/O Gate
DQ0
I/O Buffer & Logic
refresh
Column
Active
Column
pre
Decoders
Memory
Cell
Array
DQ31
Column decoders
bank select
Column Add
Counter
A0
Address buffers
A1
Address
Registers
Burst
Counter
Burst Length
A11
BA1
BA0
Mode
Register
CAS Latency
Data Out
Control
Rev. 0.5/Nov. 02
5
HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C
HY5W22F-C / HY57W283220T-C
4Banks x 1M x 32bits Synchronous DRAM
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 BA0
0
0
A11
0
A10
0
A9
0
A8
0
A7
0
A6
A5
A4
A3
BT
A2
A1
A0
CAS Latency
Burst Length
CAS Latency
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
A3
0
1
Burst Type
Sequential
Interleave
Burst Length
Burst Length
A3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
A3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5/Nov. 02
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