NJU3101
PRELIMINARY
4-BIT SINGLE CHIP TINY CONTROLLER
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GENERAL DESCRIPTION
The
NJU3101
is the C-MOS 4-bit Single Chip Tiny
Controller consisting of the 4-bit CPU Core, Input / Output
Selectable I/O ports, Program ROM, Data RAM, and
Oscillator Circuit (CR or Ceramic or X'tal). It is packaged
in 16-pin package (DIP or DMP form). Therefore it
provides a cost and space effective replacement with only
few external components for control-logic circuit using
standard logic ICs (i.e. 74HC) or other small controllers.
The
NJU3101
is suitable for battery operated
appliances because of low operating current, wide
operating voltage range, and STANDBY function (HALT
mode).
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PACKAGE OUTLINE
NJU3101D
NJU3101M
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FEATURES
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PIN CONFIGURATION
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Internal Program ROM 512 X 8 bits
Internal Data RAM
16 X 4 bits
Input / Output Port
10 lines
PA0
(Input / Output direction of each PORT is selected by the
PA1
mask option.)
High Output Current terminal (2 lines)
PA2
N-Channel FET Open Drain Type (I
OL
)
PA3
15mA at V
DD
=5V
Instruction Set
58 instructions
TEST
Subroutine Nesting
8 levels
OSC1
Pulse Edge Detector
The rising or falling edge of a pulse is selected by the mask OSC2
option.
V
SS
Instruction Executing Time
6/f
OSC
sec
Operating Frequency Range
30kHz
−
4MHz
Internal Oscillator
CR, or Ceramic, or X'tal oscillation and External clock input
STANDBY function (HALT mode)
Wide operating voltage range 2.4V
−
5.5V
C-MOS technology
Package outline
DIP16 / DMP16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
PE1
PE0
PD1
PD0
PC0
PB0
RESET
26/Mar/2001
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NJU3101
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BLOCK DIAGRAM
CPU CORE
STACK
TLUaddr
MUX
ROM
512 x 8 bits
IR
RAM
16 x 4 bits
ID
STANDBY
CONTROLLER
ALU
CPU
TIMING
GENERATOR
OSC
TEST
RESET
OSC1
OSC2
PC
X’-Reg
Y’-Reg
X-Reg
Y-Reg
AC
V
DD
V
SS
PORTA
PORTB
PORTC
PORTD
PORTE
PC0
PD0
PD1
PB0
PE0
PE1
PA0
PA1
PA2
PA3
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NJU3101
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TERMINAL DESCRIPTION
No. SYMBOL
1
PA0
2
PA1
3
PA2
4
PA3
FUNCTION
4-bit Input / Output PORTA.
Selects a terminal circuit for PORT grouped with 4 lines from
follows by the mask option.
•
C-MOS Input Terminal with Pull-up Resistance(IA)
•
C-MOS Input Terminal(IC)
•
C-MOS Output Terminal(OB)
Maker Testing Terminal with Pull-down Resistance
5
TEST
INPUT
The terminal is recommended to connect to GND.
Internal Oscillator Terminals.
6
OSC1
INPUT
Connects a device selected from the ceramic or the crystal
7
OSC2
OUTPUT
resonator, or the resistor, to these terminals for the internal
oscillator.
In the external clock operation, OSC1 is the external clock
input terminal and OSC2 is normally open terminal.
V
SS
–
Power Source (0V)
8
9
INPUT
RESET Terminal.
RESET
When the low level input-signal, the system is initialized.
10
PB0
INPUT/OUTPUT
1-bit Input / Output PORTB and PORTC.
Selects a terminal circuit for each PORT from follows by the
11
PC0
INPUT/OUTPUT
mask option.
•
C-MOS Input Terminal with Pull-up Resistance(IA)
•
C-MOS Input Terminal(IC)
•
Nch-FET Open-Drain Output Terminal with Pull-up
Resistance(OA)
•
Nch-FET Open-Drain Output Terminal(OC)
12
PD0
INPUT/OUTPUT
2-bit Input / Output PORTD.
Selects a terminal circuit for PORT grouped with 2 lines from
13
PD1
follows by the mask option.
•
C-MOS Input Terminal with Pull-up Resistance(IA)
•
C-MOS Input Terminal(IC)
•
C-MOS Output Terminal(OB)
When the ports are selected as the input terminal, PD0
operates also as RESTART signal input terminal to return from
STANDBY mode, and PD1 operates also as the Edge
Detector Terminal.
14
PE0
INPUT/OUTPUT
2-bit Input / Output PORTE.
Selects a terminal circuit for PORT grouped with 2 lines from
15
PE1
INPUT/OUTPUT
follows by the mask option.
•
C-MOS Schmitt Trigger Input Terminal with Pull-up
Resistance(IB)
•
C-MOS Schmitt Trigger Input Terminal(ID)
•
C-MOS Output Terminal(OB)
V
DD
–
16
Power Source (2.4V
−
5.5V)
Note )
INPUT/OUTPUT : Input or Output is selected by the mask option.
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
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NJU3101
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INTERNAL SYSTEM DESCRIPTION
The
NJU3101
is a C-MOS 4-Bit Single Chip Tiny Controller consisted of Original CPU Core, Selectable
Input-Output(I/O) Ports(MAX. 10 lines), Program ROM(512 bytes), Data RAM(16 nibbles), and Oscillator
Circuit which can select a type from four oscillators types(i.e. Ceramic or X'tal or CR oscillation or External
clock operation).
The CPU block in the
NJU3101
is consisted of ALU(Arithmetic Logic Unit) executing the binary adding,
subtracting or logical calculating, AC(Accumulator), four Registers, STACK allowing the 8-level
subroutine-nesting, Program Counter indicating 512 addresses sequentially, and Timing generator.
The
NJU3101
can be applied to the various markets because of the rich and efficient instruction set(58
instructions), wide operating voltage range(2.4V to 5.5V), low operating current, and STANDBY function
reducing the power supply current.
(1) INTERNAL REGISTER
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Accumulator(AC)
Accumulator(AC) is structured by the 4-bit register. It holds a data or a result of calculation, and
executes the shift-operation(ROTATE) or the data transference between the other registers and Data
Memory(RAM).
Accumulator condition is unknown on the “RESET” operation.
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X-register(X-reg)
X-register(X-reg) operates as the 4-bit register.
The X-reg condition is unknown on the “RESET” operation.
Y-register(Y-reg)
Y-register(Y-reg) operates as the 4-bit register or the RAM address pointer.
The Y-reg condition is unknown on the “RESET” operation.
X'-register(X'-reg)
X'-register(X'-reg) operates as the 4-bit register or a part of Program Memory(ROM) address pointer for
looking data in the ROM(TRM instruction) up function.
The X’-reg condition is unknown on the “RESET” operation.
Y'-register(Y'-reg)
Y'-register(Y'-reg) operates as the 4-bit register or the peripheral register number(PHYn) pointer.
The Y’-reg condition is unknown on the “RESET” operation.
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•
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(2) INTERNAL FLAG
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RPC flag(RPC)
RPC flag(RPC) changes the instruction table. Several instructions perform either of the dual tasks in
accordance with the RPC flag condition. The RPC flag condition selects either of two couples of
registers which are X- and Y-reg, or X'- and Y'-reg. X- or Y-reg is selected when the RPC flag condition
is "0"(RPC=0). X'- or Y'-reg is selected when the RPC flag condition is "1"(RPC=1). The RPC flag
condition is set to "1"(RPC=1) by SRPC instruction, and is set to “0”(RPC=0) by RRPC instruction.
The RPC flag condition is set to “0” on the “RESET” operation.
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CARRY flag(CY)
When the carry occurs after the adding calculation, the CARRY flag(CY) condition is set to "1"(CY=1),
and when no carry, the CY flag condition is set to "0"(CY=0). When the borrow occurs after the
subtracting calculation, the CY flag condition is set to "0"(CY=0), and when no borrow, the CY flag
condition is set to "1"(CY=1). The bit-operation instruction operates the bit data rotation on the CY flag
combined with Accumulator or the other register.
The CY flag condition is set to "1"(CY=1) by SEC instruction and is set to "0"(CY=0) by CLC instruction.
The CY flag condition is kept until the end of the next instruction executing cycle. The CY flag condition
is unknown on the “RESET” operation.
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NJU3101
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STATUS flag(ST)
STATUS flag(ST) is the conditional flag in accordance with the result of the instruction execution. Its
condition is in accordance with follows:
1) to be same as CY flag condition.
2) to be set the condition to "0"(ST=0) when the result of the logical calculation(AND, OR, XOR,
YNEA) is zero.
3) to be set the condition to "0"(ST=0) when the result of the comparison(CMP) is zero.
However, ST flag condition is always set to "1"(ST=1) except above three.
ST flag controls the branch operation. Branch instruction does not branch when ST flag condition is
"0", and branches when ST flag condition is "1". ST flag condition is kept until the end of the next
instruction executing cycle.
The ST flag condition is unknown on the “RESET” operation.
(3) FUNCTIONAL BLOCK
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ARITHMETIC LOGIC UNIT(ALU)
ARITHMETIC LOGIC UNIT(ALU) is a 4-bit binary paralleled calculation circuit operating binary addition,
binary subtraction, comparison, logical AND, logical OR, exclusive OR, and SHIFT(Rotation). And it also
can detect CARRY, BORROW or ZERO in accordance with the result of each calculation.
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PROGRAM MEMORY(ROM)
PROGRAM MEMORY(ROM) consists of 8 pages, and a page consists of 64 bytes memory capacity.
Therefore the
NJU3101
prepares the 512-byte ROM for the application program. The ROM address is
indicated by the Program Counter(PC).
[PROGRAM MEMORY AREA]
(Addresses)
000H
040H
080H
Program Start Address
Page0
Page1
Page2
(Addresses in the page)
00H
64 Instruction Words
3FH
180H
1C0H
1FFH
Page6
Page7
* 8 Bits / Instruction Word
64 Instruction Words / Page
8 Pages / ROM
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嵌入式系统
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