HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
Document Title
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Correct Summary description & page.7
- The Cache feature is deleted in summary description.
- Note.3 is deleted. (page.7)
2) Correct table.5 & Table.12
3) Correct TSOp1, WSOP1 Pin description
- 38th pin has been changed Lockpre
4) Add Bad Block Management & System Interface using CE don’t care
5) Change TSOP1, WSOP1, FBGA package dimension & figures.
- Change TSOP1, WSOP1, FBGA package mechanical data
- Change TSOP1, WSOP1 package figures
1) LOCKPRE is changed to PRE.
- Texts, Tables and figures are changed.
2) Change Command Set
- READ A and B are changed to READ 1.
- READ C is changed to READ 2.
3) Change AC, DC characterics
- tRB, tCRY, tCEH and tOH are added.
4) Correct Program time (max)
- before : 700us
- after : 500us
5) Edit figures
- Address names are changed.
6) Change AC characterics
tRP
Before
After
30
25
tREA
35
30
History
Draft Date
Sep. 2004
Remark
Preliminary
0.1
Nov. 29. 2004
Preliminary
0.2
Mar. 03. 2005
Preliminary
Rev 0.6 / Nov. 2005
1
HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
Revision History
Revision
No.
History
1) Change AC Characteristics (1.8V device)
tRC
Before
After
50
60
tRP
25
40
tREH
15
20
tWC
50
60
tWP
25
40
tWH
15
20
tREA
30
40
- Continued -
Draft Date
Remark
2) Change AC Parameter
tCRY(3.3V)
tCRY(1.8V)
50+tr(R/B#)
60+tr(R/B#)
tOH
15
10
0.3
Before
After
50+tr(R/B#)
60+tr(R/B#)
Jun. 13. 2005
Preliminary
3) Add Read ID Table
4) Edit Automatic Read at Power On & Power On/Off Timing
- Texts & Figure are Changed.
5) Insert the Marking Information.
6) Change 128Mb Package Type.
- FBGA package is deleted.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
1) Delete the 1.8V device’s features.
2)
Change AC Conditions table
3)
Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit Copy Back Program operation step
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
1) Correct PKG dimension (TSOP, USOP PKG)
CP
0.5
Before
After
0.6
0.050
0.100
Nov. 07. 2005
Sep. 02. 2005
0.4
Jul. 26. 2005
1) Correct USOP figure.
Rev 0.6 / Nov. 2005
2
HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
- Device Code
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes
: HY27US08281A
- x16 device: (256 + 8 spare) Words
: HY27US16281A
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27US(08/16)281A-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)281A-T (Lead)
- HY27US(08/16)281A-TP (Lead Free)
- HY27US(08/16)281A-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27US(08/16)281A-S (Lead)
- HY27US(08/16)281A-SP (Lead Free)
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
Memory Cell Array
: HY27USXX281A
= (512+16) Bytes x 32 Pages x 1,024 Blocks
= (256+8) Words x 32 pages x 1,024 Blocks
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 10us (max.)
- Sequential access: 3.3V device: 50ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
Rev 0.6 / Nov. 2005
3
HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27US(08/16)281A series is a 16Mx8bit with spare 4G bit capacity. The device is offered in 1.8V Vcc
Power Supply and in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 1024 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected
Flash cells.
A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP# input pin.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-
tiple memories the RB# pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27US(08/16)281A extended reliability of 100K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the
code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-
tion.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,
Read ID2 extension.
The Hynix HY27US(08/16)281A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP1 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27US08281A
HY27US16281A
ORIZATION
x8
x16
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1/48USOP1
Rev 0.6 / Nov. 2005
4
HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE#
RE#
WE#
WP#
RB#
Vcc
Vss
NC
PRE
Data Input / Outputs (x16 Only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Power-On Read Enable, Lock Unlock
Table 1: Signal Names
Rev 0.6 / Nov. 2005
5
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